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ADC128S102EVM: Crosstalk across ADC channels

Part Number: ADC128S102EVM
Other Parts Discussed in Thread: ADC128S102

I am using the ADC128S102EVM to evaluate the ADC128S102 and I am experiencing crosstalk between channels.

My test setup is fairly simple.

I have connected the EVM board to an STM32F7 uC and I am simply alternating scans between channel 0 and channel 1 and I am injecting DC voltages on each channel and measuring the effect on the alternate channel. The DC sources are buffered, low impedance sources. I am running SCLK at 16MHz, and I am pulling CS high for 1us between samples. Vdd = 3V3 and VA = 5.148V which is well filtered and clean

When I inject 0V on Ch0 and Ch the output reading on both channels is 0 as expected.

However, when I inject 3V3 on Ch1 and 0V on Ch0 the readings are as follows: Ch =  2624 (3.298V) and Ch0 =  0009 (11.3mv) The analog inputs are reading 0.000V on a Fluke 179.

I thought that this might be due to the kick back filter (I am using the default on the EVM board which is a 48kHz cut-off, [200R and 10nF RC Lowpass]).

In order to test this I lowered the SCLK frequency 8MHz to increase the acquisition time, this has had little to no effect, I read 0008 instead of 0009 which I am putting down to an expected variation of 1 bit.

After lowering SCLK, I am now doing a dummy scan on each channel and discarding the result. Eg, I scan Ch0 throw away the result, then scan again and keep the value. Then I scan Ch1, throw away the result and scan it again to store the value. I repeat this cycle. I would expect this to remove the possibility of charge transfer from the sampling capacitor when switching channels affecting the readings. There has been no improvement after this change. As I lower Ch1 to 1V Ch0 reads 0003 and when Ch1 = 500mV, Ch0 reads 0001 so the readings on Ch0 seem to be related to Ch1.

Things to note, As the EVM board is connected to an STM evaluation board the layout is not ideal. There is some noise present, however, if that was causing the readings I would expect to have a reading when both inputs are 0V, is this an incorrect assumption?

Any assistance will be greatly appreciated. 

Thanks in advance!

  • Hello,

    Have any changes been made to the EVM?

    How are the input connections made to the EVM? Note that the EVM has header pins to apply the input voltage, this could lead to the inputs interacting at this point of contact, thus good connections should be used.



  • Hi Cynthia,

    The only chnages to the EVM have been to solder a clean +5V reference to for VA and a +3V3 supply and SPI lines have been connected to the board so that I can control the ADC. The SCLK, MOSI and CS lines have series termination at the uC side and these all look quite clean at the ADC.

    The inputs are coming from two buffered DC sources which are brought to the pin headers on the EVM with shielded cables. These cables are then soldered onto the header. Unused inputs have been grounded. when the signal input headers are left open, the inputs couple into eachother as I would expect but once each input is driven by a low impedance this is not a problem, I cannot measure any coupling at the ADC input so I believe the issue to be caused either internally within the ADC or by charge transfer from the sampling capacitor.

    Interestingly, after running tests on the EVM to test the filter, I first changed it to 200R and 470pF, the crosstalk increased as I expected. Keeping the 470pF capacitor and lowering the resistance improves the crosstalk levels but noise increases due to the increased bandwidth. Removing the ADC input filter on both channels completely eliminates the crosstalk but there is up to 6LSB of noise so it looks as though I need to find the correct balance for my application.


  • Hello,

    Apologies for the late response. In your first set up, you were trying to go from two voltages with a large delta, paired with a too large capacitor (10n). this likely meant the ADC was not settling in time. The large cap was not driven, which meant the sample and hold circuitry not driven correctly and resulted in inaccurate results.

    Once you changed the RC to a smaller ca value, the input was more able to drive the voltage between conversions

    TI has great tool to help find the correct RC value to drive the ADC input. the Analog Eng Calculator

    I went ahead and put in the worst case scenario, which would be the fastest sampling rate. SCLK of 16Mhz, and the acquisition time of 3*SCLK.

    This gave a R range of 13 to 108 ohms, and an optimal C value of 680pF (though an acceptable range is 330p to 1nF)

    Also note that to run the device at max sampling rate, the input will need at leas 17MHz bandwidth device (GBW).

    if the device is operating at lower sampling rate, then a slower op amp can be used.