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ADS127L01: Is daisy chaining 2 ADS127L01s at 512kHz samplerate possible?

Pavel Hofman1
Prodigy 170 points
Part Number: ADS127L01

Hi,

Please is it possible to daisy chain 2 ADS127L01 in frame sync slave mode at 512kHz samplerate? The datasheet specifies min. period of SCLK at 40ns which is 25MHz - enough for 384kHz (64bits per frame period). 512kHz requires SCLK at 32.768MHz.

Thanks a lot for confirming this limit.

Best regards,


Pavel.

  • 0
    TI__Guru 66186 points

    Hello Pavel,

    Thank you for your post.

    Technically, a 25-MHz SCLK is fast enough to read from both devices at 512 kSPS, but only if you do not read the 8-bit STATUS word. This would reduce the frame size to only 48 bits. You would first need to program the CONFIG register in SPI mode before switching to Frame-Sync mode to disable the STATUS word. Understandably, this is more complicated and may not be feasible for your application. If you can do it, then an SCLK frequency of 24.576 MHz is just fast enough to read all 48 bits within each frame at 512 kSPS.

    If you require reading all 32 bits, then I'm afraid you will need to reduce the output data rate.

    By the way - we have an Excel calculator tool on the ADS127L01 product folder, which includes a tab dedicated to calculating the number of devices possible in a Cascaded or Daisy-Chain Configuration:

    https://www.ti.com/tool/ADS127L010-EXCEL-TOOL-CALC

    Best regards,

  • 0 in reply to Ryan Andrews
    Prodigy 170 points

    Hi Ryan,

    Thank you for your expert advice.

    I am trying the Excel calculator and it keeps saying "For Frame-Sync interface, SCLK/CLK must equal 1/2^n". Therefore it does not accept CLK at 16.384MHz/OSR=32/samplerate=512kHz and SCLK at 24.576MHz for the 2x24bit transfer. Please is there any way?

    Thanks for your patience.

    With regards,

    Pavel.

  • 0 in reply to Pavel Hofman1
    TI__Guru 66186 points

    Hello Pavel,

    Let me confirm with a digital designer whether this warning is accurate. The real concern is keeping SCLK and FRAME synchronized such that each frame contains exactly the same number of SCLK periods. The same note is written in section 8.5.2.2.2 in the ADS127L01 data sheet. If you click "continue" or "yes" in the Excel tool, it will let you put any value of SCLK in the cell.

    Best regards,

  • 0 in reply to Ryan Andrews
    TI__Guru 66186 points

    Hi Pavel,

    If you can disable the STATUS byte with an SPI register write before entering frame-sync slave mode, then there is no issue with using a 24.576-MHz SCLK to daisy-chain two ADS127L01 devices. This would allow you read exactly 48 bits per frame at 512 kSPS. The note in the data sheet assumes that most customers will exclusively use frame-sync mode and will not have the ability to read/write registers prior to data collection.

    If you cannot disable the STATUS word, then you may need to consider the Cascaded configuration and read the data from both devices into two separate MISO pins on your host controller. The FSYNC and SCLK signals would be shared, while /CS and DIN would be tied to ground (excuse the mistake in Figure 104 which shows DIN connected to MOSI). With the Cascaded configuration, you only need to send 24 SCLKS per frame and you would not clock out the last 8 bits. The length of the frame must contain 32 master CLK periods @ OSR = 32. Therefore, your SCLK frequency in this case would be 12.288 MHz and your CLK frequency will be 16.384 Mhz, giving you exactly 24 SCLK periods and 32 CLK periods in each frame at 512 kSPS. The rising edge of FSYNC will launch the MSB of the new data as long as you have the correct number of master CLK periods in the frame to complete the conversion, even without reading the complete 32-bit frame.

    Best regards,

  • 0 in reply to Ryan Andrews
    Prodigy 170 points

    Hi Ryan,

    Thank you for the very positive answer. I can switch GPIO functions on my MCU from PCM functions (I2S lines) to general GPIOs and use software SPI to configure the ADC registers, before switching back to PCM/I2S.

    Please, when programming the registers via SPI :

    * does the DRDY/FSYNC pin have any purpose?

    * is the CLK signal important, does it have to be somehow synchronous to the SPI SCLK? Does it have to be running during programming the registers via SPI?

    I am considering using one of TI's  ultra-low jitter clock generators https://e2e.ti.com/support/clock-and-timing/f/48/t/906747 f the clock chip allowed tri-state outputs (to release the SCLK line for the MCU SPI), the above scheme would require just software support in the MCU, no extra gates.

    Ryan, thank you for your help.

    Best regards,

    Pavel.

  • 0 in reply to Pavel Hofman1
    Prodigy 170 points

    Ryan, please do I understand correctly that jitter on the data-collecting SCLK signal is not critical for conversion precision? If the clock circuit does not support tri-state outputs, I would have to feed SCLK through another gate to switch between the high-speed frame-sync SCLK by the external clock circuit and slow bit-banged SPI SCLK from the MCU for setting the registers.

  • 0 in reply to Pavel Hofman1
    TI__Guru 66186 points

    Helo Pavel,

    In SPI Mode, the /DRDY/FSYNC pin serves as a data-ready (/DRDY) interrupt function. This is only used to indicate to the host that new data is ready to read and does not affect register read/write access.

    The CLK signal is the master clock for the device and is required to remain free-running for both analog and digital functions at all times.

    The jitter on the SCLK is not significant as long as there is enough margin on the rising/falling edges to meet the timing specifications. Data is latched on the SCLK rising edge and changed on the SCLK falling edge.

    Best regards,

  • 0 in reply to Ryan Andrews
    Prodigy 170 points

    Ryan, thanks a lot for the important details. Please do I understand correctly that when writing registers via SPI the SCLK signal can be asynchronous to the CLK, i.e. bit banging GPIOs (software SPI) on the MCU could be used for the initial setup?

    Also please is there a minimum frequency for the SPI SCLK when writing the registers? I think the datasheet gives just the upper limit (min period time) but people usually do not use slow software SPIs :-)

    I very much appreciate your help.

    Regards,

    Pavel.

  • 0 in reply to Pavel Hofman1
    TI__Guru 66186 points

    Hi Pavel,

    Yes, SCLK and CLK can be asynchronous. Please check the timing diagrams and specifications in the data sheet. There is no minimum SCLK, so that's not a concern.

    Best regards,