DAC3162: If the two channel output updated simultanously?

John11513

Part Number: DAC3162

Hi team,

My customer asked me a question about DAC3162. As a DDR input and DACA and DACB sample input are interleaved. The DACA data is latched at rising edge and DACB is latched at falling edge. However the datasheet does not explain at which edge the outputs are updated. If the output is updated at the same time when data is latched that will result phase delay between two channels. I searched for answer in forum and found same question was asked before. While it seems there is not final conclusion. (Some Tier said the two channels are updated at same time, however customer's test did not support this.)

Thank you!

John

over 3 years ago

0 John11513 over 3 years ago

TI__Expert 5360 points

Hi,

Any response about this question?

Thank you!

John

0 Neeraj Gill over 3 years ago

TI__Mastermind 20541 points

Hi John,

Both of the DAC outputs should update simultaneously.

Regards,

Neeraj

0 John11513 over 3 years ago in reply to Neeraj Gill

TI__Expert 5360 points

Hi Neeraj,

At which clock edge the two DAC outputs are updated?

Thank you!

John

0 RJ Hopper over 3 years ago in reply to John11513

TI__Mastermind 18065 points

John:

Internal to the DAC, the A path uses an additional register that is clocked by an inverted version of the data clock. With this register, the final value for A data would be the falling edge of the clock, which is the same edge used by the B data. This ensures the output data is synchronized and is transparent to the user.

--RJH

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DAC3162: If the two channel output updated simultanously?