• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 47 subscribers
  • Views 1472 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC8801 POR threshold and register data retention

Ron Hansen
Prodigy 20 points
Other Parts Discussed in Thread: DAC8801

I am trying to characterize some power up/down behavior we are experiencing with in an application using the DAC8801.  Upon a power cycle, approximately 1-2 sec powered down, sometimes the DAC retains it's last issued value.  On power down, we have observed that the VCC supply decays quickly to approximately 1.3Vdc and then slowly decays toward 0V at a rate of ~0.2Vsec afterwards.  So we suspect that the DAC is not completely executing a power down on power interupts of several seconds.  Can you please give me the specifications for the POR threshold on the DAC8801.

If the supply holds up slightly above the POR threshold, is it posible for the registers to begin losing their data, where some bits are retained and others are lost?

In addition, when the supply has decayed well below ~0.9Vdc, we sometimes don't get a complete reset of the DAC.  Is it possible that although the DAC register is filled with zeros on power up, the shift register is not reset and could have random data on power up?

  • 0
    TI__Guru**** 168285 points

    Hi Ron,

    Are you working with John and Hiroshi on this project?  We've have a few conversations going on through different channels at the moment and we're trying to consolidate everything now.  Will post back once everything is finalized.

  • 0 in reply to Tom Hendrick
    Prodigy 20 points

    Yes.  I wasn't aware that they had already initiated conversations with you.  They have updated me a little, but I'm sure they had discussed the data retention question wth you.  Can you please respond to it.

  • 0 in reply to Ron Hansen
    TI__Mastermind 43915 points

    Hi Ron, 

    I believe this has been resolved, but to quickly update you on this -


    The DAC8801 basically has two registers, the shift register and the DAC data register. The POR only resets the DAC data registers and not the DAC shift register. Additionally, the DAC uses the rising edge of /CS to update the contents from the shift register into the data register. Therefore, if the DAC is powered down and powered back up with /CS low, the DAC data register will be updated with whatever contents are in the shift register on the next /CS rising edge. This is what was being seen. They were powering up the DAC with /CS low and then bringing it high a few ms later and the outputs are updating to whatever is in the shift register. Generally, I would expect the contents of the shift register to go to 0x0000 or 0xFFFF upon power up(as the shift register is not flash memory) but if there is any residual charge on any of the pins, it may be enough to keep the shift register active to hold the previous value. Regardless, the point is that the POR does not reset the shift register. We proposed three work around solutions for them -

    1. Power on the DAC with /CS held high

    2 . Power on the DAC with the /CS delay, then immediately bring /CS low and write 0x0000 to the part to set the output to 0V. This would cause the output to read -5V for a small period

    3. Power on the DAC with/CS held low, send 16 SCLKs with DIN held low clearing out the shift register. Then bring /CS high. Since, the output only updates on the rising edge of /CS, this would avoid any period with the output reading 5V. I am just not sure if they can power up their microcontroller with /CS held low.

    Regards,

    Tony Calabria