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DAC3482: Data Pattern Checker Test not working

Part Number: DAC3482

Although,I'm not getting fifo synchronoisation alarms,I'm getting IO test reults in 0x4 as 0xffff,and corresponding IOtest alarms in 0x5 of DAC
Btw,I followed the provcedure by enabling IO test 

Please suggest any solution

  • Hi,

    This means the pattern expected from the ones programmed in the DAC3482 is different than the pattern actually being send from the FPGA

    Please advise the test result when you send all 1's and 0's and program the expected pattern in the DAC3482 register. This is the easiest way for a quick check.

    Please also elaborate exactly your test methodology. We are not able to proceed further based on your information above. 


  • we will close this forum post for now. please feel free to post more information to reopen the thread again. 


  • Hi Kang,

    Thanks for your reply.
    I will eloborate the things below
    Actually we've two 3482 DAC's on the same board(both being independent),So Single source is used for fifo synchronisation
    ->Data clocks:75Mhz,150Mhz,300Mhz,600Mhz with interpolation factors 16,8,4,2 respectively
    ->Ref DACCLK to DAC pll:150Mhz and generated 1200 DAC_CLK internally to DAC

    -> DAC's are used in 16bit word format

    1.FIFO Synchronisation
     First thing I tried to to fifo syncroninsation.Initially I used FRAME signal for that purpose and found the fifo away and fifo collision(sometimes) in one of the DAC.
    Later I tried using SYNC signal of DAC and successfully removed the fifo alarms with.If we run at higher speeds  and very low speeds(i.e,DATACLK600Mhz and 75Mhz),fifo alarms are still coming but using the algorithm given in the doc by TI for achieving FIFO synchronisation,I'm able to remove them.So,till now no problem for synchronisation


    After fifo synchronisation,I tried to run the IO test by giving IO_test enable and same pattern which is programmed inside DACs IO_test_pattern registers ,is used as training pattern from FPGA .
    Here also,I'm giving the same SYNC signal for finding first word of the pattern
    I'm getting 0xffff from 0x4(IOtest results) register of DACs and corresponding alarm is raised in 0x5 reg of DACs
    Sir,I also tried giving all 0's and all 1's to DACs and the same is programmed in DACs,but still I'm getting IO test as failed in all bits.
    So I want to know where I'm missing and why this is happening?

  • Lenin,

    If you are sending all LVDS logic HI (1's) or lows (0's), you will need to make sure IO_Pattern0 to IO_Patter7 are all programmed to 0xFFF for all 1's or 0x0000 for all 0's.

    If this is not passing, then there is something wrong with your whole setup. I recommend you actually probe the LVDS pattern to see if proper signals are being send to the DAC3482.

    Be sure to clear the alarms by writing 0s first and then read back.


  • Hi Kang,
    If I'm sending defaut pattern given in DAC,I'm getting IOresults(0x4) as 0xffff
    If I'm sending all 0's to dac( after keeping 0's in IO_pattern0 to IO_pattern_7),,I'm getting IOresults(0x4) as 0x1fff
    If I'm sending all 1's to dac( after keeping 1's in IO_pattern0 to IO_pattern_7),,I'm getting IOresults(0x4) as 0x0eee

    I'm unable to infer anything from this.
    Btw,I'm sure that data lines are not reversed and not send in 2's compliment form(as mentioned in 0x2 register)

    Please help me to solve this

  • Hi Lenin,

    Could you probe the LVDS lines with differential probe to see if there are shorts/open on the LVDS connection? The result is consistent between all 1's and all 0's. The first DATA[15:13] seem to be getting the correct level, but the rest of the LVDS lines are not

    If you have MRQFN package on your board, please check the soldering through x-ray. We have encountered bad solder from customers where the internal pins are shorted, and caused similar results

    Manufacturing guidance of the MRQFN are listed below


  • Hi Kang sir,
    Actually we are using three DAC3482's on same board.
    We are facing the same issue as mentioned by me in previous post(i.e. 0x4 readings while sending 0's and 1's) for all the three DAC's.
    How can we understand that?I'm confident enough that we are following proper procedure for IO test
    Thanks in advance for your reply

  • Hi Lenin,

    I cannot provide further help until you actually probe each of the lines to check for the voltage level. You need to make sure the lower LVDS bus are actually configured as LVDS level from your FPGA. There is not enough information to work on this problem. 

    As you have mentioned, this is a very simple test. The mere fact that a constant ones or zeros are giving error indicating bus failure. You will need to probe the signal to get better understanding. 

    Please provide actual scope shots (differential probe) to plot similar to figure 75 of the datasheet. You may also try 0x5555 and 0xAAAA (0/1 toggling) pattern and measure on the scope to check for setup/hold time.