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ADS8332: problem with ads8332 resolution reading

Part Number: ADS8332
Other Parts Discussed in Thread: REF6050, REF02

Hi,

I try to use an ADC ADS8332 with SPI communication.

It seems to be work great.

I am able to configure the CFR register (the config is 0b011111111111);.

I tried also to read data value with manual trigger. But I have a problem with this part. I read well a 16 bits data but I have no noise on the data. And there is step on the data like the curve I join

I tried to insert some delay to slow down the acquisition process. But i have always the same results.

I have also the problem in automatic trigger.

Moreover sometimes, the EOC doesn't go to low when I put CONVST at low. So, I have to put back CONVST at high and low.

This is the code which I use to read channel 1 for example

uint16_t adc_read_channel_1()
{

    long t = millis;
    while(millis - t <5);
    
    CONVST_Clear();
    
    while(EOC_INT_CDI_Get()!=0)
    {
        CONVST_Set();
        CONVST_Clear();
    }
    
    while(EOC_INT_CDI_Get()==0);
    CONVST_Set();
    
    
    
    uint8_t send[4] =  {READ_DATA,0,};
    uint8_t receive[3] = {0};
    CS_ADC_Clear();
    SPI1_WriteRead(send, 2, receive, 3);
    CS_ADC_Set();
    
    if(receive[2] ==32)
        SYS_CONSOLE_PRINT("%i \n\r",((uint16_t)(receive[0]<<8) + receive[1]));
    
    
    return ((uint16_t)(receive[0]<<8) + receive[1]);
}

And the schematic

Thank you for your help and sorry for my bad english!

Best regards,

Anthony

  • Hello Anthony,

    It appears that you have a timing issue in your communications.  If you could capture the waveforms using a logic analyzer or an oscilloscope, that would be helpful.

    If I am reading your code correctly, it appears you have /CONVST inverted.  /CONVST should be held high, and when you are ready to start a conversion, set it low and then high again.  Wait for EOC to return high, and then read your data.  Also, you are trying to read data while converting (EOC LOW), which requires that you read your data before the end of conversion.  Since I cannot tell what frequency you are using, I suggest you READ WHILE SAMPLING, per Figure 1 in the datasheet.

    Please adjust your code as follows:

    1.  Set /CONVST low, and then return high to start the conversion.
    2.  Delay ~1uS
    3.  Monitor EOC and wait for it to return HIGH
    4.  Once EOC returns high, take /CS low and clock the conversion result (16SCLK with SDI 0x1101000000000000b)
    5.  Return /CS HIGH
    6.  Repeat Step 1

    Also, the REF02 output cannot directly drive the ADC inputs and get anywhere near the noise performance of the ADC.  You should either add a reference buffer, per Figure 51 in the datasheet, or use the REF6050, which includes a high speed buffer suitable for driving the REF input of the ADS8332.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Hello,

    thank you for your help.

    I change the code like this.

        long t = 0;
        CONVST_Clear();  
        CONVST_Set();
        
        
        
        t = micros;
        while(micros - t <10);  //wait 10us
        
        while(EOC_INT_CDI_Get()!=1)SYS_CONSOLE_PRINT("WAIT");
        
        uint8_t send[2] =  {0xD0,0x00};
        uint8_t receive[3] = {0};
        CS_ADC_Clear();
        SPI1_WriteRead(send, 2, receive, 3);
        CS_ADC_Set();
        
        if(receive[2] ==32)
            SYS_CONSOLE_PRINT("%i      %i    %i %i\n\r",((uint16_t)(receive[0]<<8) + receive[1]),receive[0],receive[1],receive[2]);
        
    

    And I have same results

    And there is the tab of data (value of adc(MSB+LSB),   MSB , LSB, TAG)

    We have only three possible value on LSB.... I don't know why.

    3107 12 35 32
    3139 12 67 32
    3331 13 3 32
    3331 13 3 32
    3587 14 3 32
    3843 15 3 32
    4099 16 3 32
    4227 16 131 32
    4355 17 3 32
    4611 18 3 32
    5187 20 67 32
    5187 20 67 32
    5251 20 131 32
    5251 20 131 32
    5379 21 3 32
    5635 22 3 32
    5763 22 131 32
    6147 24 3 32
    6275 24 131 32
    6403 25 3 32
    7235 28 67 32
    7235 28 67 32
    7235 28 67 32
    7299 28 131 32
    7299 28 131 32
    7427 29 3 32
    7427 29 3 32
    7683 30 3 32
    7939 31 3 32
    8195 32 3 32
    8195 32 3 32
    9283 36 67 32
    9283 36 67 32

    I will try to make a capture of signals with logic analyzer.

    Anthony

  • I make a capture with a digital analyzer. 

    And I read with my microcontroller

    19523 76 67 32

    19523 76 67 32

    19523 76 67 32

    19523 76 67 32

    19523 76 67 32

    19523 76 67 32

    19523 76 67 32

    19523 76 67 32

    19523 76 67 32

    19523 76 67 32

    19523 76 67 32

    19523 76 67 32

    It seems to be correct?

  • Hello Anthony,

    The timing between EOC, /CS, and SCLK all look correct.  However, I cannot tell if the timing requirements are met for SDI relative to SCLK edge.

    Can you provide a zoomed in version of the above data showing the first 16 SCLK's and the SDI line?

    Also, what is the frequency of SCLK?

    Regards,
    Keith