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DAC80004: DAC80004 channel output cannot be updated

bart van straaten
Prodigy 100 points
Part Number: DAC80004

Sometimes the a DAC80004 output channel cannot be updated
The value remains the reset value although new values are written and loaded (??) by the synchronous LDAC mode

My idea: the state of the DAC appears to me as a kind of latch-up of the channel, because the whole DAC80004 environment has to be powered down and up again to resolve this state.
Can this be the case when the SPI interface signals becomes active before the 5V supply is present on the device?

The POR is connected to the 5V supply, the LDACn is connected to 0V.
The SPI and CLR inputs are connected to FPGA pins via a galvanic coupler with 3V3 output
These pins are '1' (3V3) during power-up and configuration of the FPGA and before the DAC80004 5V supply becomes available.

We found also problems when the POR signal was connected to the 3V3 instead of the 5V at this moment. In that case the 3V3 was present before the 5V.

Another question to make sure: What should I do with the LDACn pin when want to use the SW load only?

  • 0
    TI__Mastermind 18546 points

    Hi,

    Can you please share your schematics?

    As I understand, SPI signals are active before your DAC VDD is up right?  we have ESD protection diodes connected to each of the digital IO pin to DVDD, if SPI signals are active before VDD is up, it can forward bias the diode  and can cause huge currents to flow, which can create temporary latch up conditions.

    In SW mode LDAC, depends on bit (D03 – D00), If the LDAC register bit is set to 1, it overrides the LDAC pin (the LDAC pin is internally tied low for that particular DAC channel), and this DAC channel updates synchronously after the falling edge of the 32nd SCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is controlled by the LDAC pin. You can tie LDAC to ground if you are not using the LDAC pin functionality.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 100 points

    Hi AK,

    I have added parts of the schematic in the DOCX. I may not provide the full set of schematics. In the DOCX is also a measurement related to the 5V. 

    About the SW load, in de datasheet mentions for command 3 "Write to buffer n and update all DACs (Software LDAC)".  What is the tolerance between the channels in the simultaneous SW load?

    DAC80004_Schematic.docx

  • 0 in reply to bart van straaten
    TI__Mastermind 18546 points

    Hi,

    Schematics looks fine to me. Regarding your question, Can you please be more specific on what do you mean by tolerance between channels?

    Also while powering up, make sure that digital signals are not active before power supplies are ramped up.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 100 points

    Dear AK,

    My expectation of the update tolerance expectation with a SW load between the DAC channels is less than 100 nsec.

    I have still no simultaneous update of the DAC's as you can see in the added doc file.

    The time between the outputs and the programming of the channel A and C with SW load is more or leass equal, 1.4 usec versus 1.256 usec.

    In the file you found also pictures of the data streams and signal timing.

    Is there something wrong in the way I want to activate the SW load or are my expectations to high?

    Thx, so far for your input.

    DAC80004_SW_Load.docx 

  • 0 in reply to bart van straaten
    Prodigy 100 points

    Hi AK,

    Did you have a look and can you give me advise?

    Or do you need more info?

    Bart

  • 0 in reply to bart van straaten
    TI__Mastermind 18546 points

    Hi,

    In SW LDAC and HW LDAC, simultaneous update of DAC output is provided. As I see from your doc, you are loading DAC registers for B & C , and giving SW LDAC to update the outputs simultaneously right? This should work as intended in the datasheet and your expectation of less than 100ns is absolutely correct.

    As a debug, can you write into B & C register and issue HW LDAC (asynchronous update by pulling LDAC pin low ) to see both are updated simultaneously?

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 100 points

    Yes AK, you  are correct and 100nsec fine.

    The SW update is given when programming the C register.

    But it is impossible to access the HW LDAC. As you can see in the schematic the pin is "hardwired" to GND_A.

    Is there another way to verify? 

    I still have doubts about the HS LDAC pin functionality.  It seams to me the synchronous mode is some how active. 

    Copied form the data sheet

    "For such synchronous updates, the LDAC pin is not required, and it must be connected to GND permanently or asserted and held low before sending commands to the device."

    Should pin not be continuously '1' when you want to update all DAC with the SW load?

    Regards. Bart

  • 0 in reply to bart van straaten
    TI__Mastermind 18546 points

    Hi,

    For software/Asynchronous updates initial state should be high. So in your case, if you want SW load, I believe LDAC should be pulled high and depends on the state of the bits , device will internally pull to low when you give software update command.

    Since in your schematics, its permanently tied to ground, you cannot have this option, unless you do some wiring.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 100 points

    Hi,

    Today I had a hangup of the channels A and D. The channels could be programmed (checked with a read back of the buffer) but the outputs didn't follow.

    Are there issues know about this kind of behavior?

    The only thing that helps, is switching off and on the system in which the DAC is used.

    Bart

  • 0 in reply to bart van straaten
    TI__Mastermind 18546 points

    Hi,

    There is no known issues with device. Did you check device supply current when the output hangup?

    I am suspecting some kind of power supply glitch. The fact that power cycle helped to come back to normal state suggests that.

    please check and let me know.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Prodigy 100 points

    Hello,

    The power supply glitch hint is indeed the cause of the problem. It normally appeared on the first Quad DAC in our system after restarten a process running at the PC. During the restart some power supplies were switched of and on, but the cycle was to short to ensure a good internal DAC power on reset. The voltage only dropped to 2V and according fig 52 of the data sheet to 0.7V for 1ms. By changing the order of power supply switching the hang-up moved to the second Quad DAC in the system. Solution: the supplies remain on during the process restart on the PC.

    For the not simultaneously switching via a SW load a demo board is ordered to investigate what should be changed. If this issue can be left open I can report back to you what problem was.

    AK, thx for your support till now.

  • 0 in reply to bart van straaten
    TI__Mastermind 18546 points

    Hi,

    Glad to know that your problem got solved. Once you have results of the SW demo board, you can open a new thread.

    Regards,

    AK