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ADS5421: ads5421

Other Parts Discussed in Thread: ADS5421

Is it required to place a buffer between FPGA and ADC even when it has a tri sated output feature

  • Mohammad,

    It is recommended to keep the capacitive loading on the data output lines as low as possible, preferably below 15pF.

    Higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. For example, with a

    typical output slew rate of 0.8V/ns and a total capacitive loading of 10pF (including 4pF output capacitance, 5pF input

    capacitance of external logic buffer, and 1pF PC board parasitics), a bit transition can cause a dynamic current of

    (10pF 0.8V/1ns = 8mA). These high current surges can feed back to the analog portion of the ADS5421 and adversely

    affect the performance. If necessary, external buffers or latches close to the converters output pins can be used to

    minimize the capacitive loading. They also provide the added benefit of isolating the ADS5421 from any digital activities on

    the bus coupling back high-frequency noise.

    The need for a buffer is usually related to the trace length between the ADC and the FPGA. If the parts are only a couple of inches away, the buffer is probably

    not required. You may want to simulate your trace impedance before deciding whether or not to add a buffer.

    Regards,

    Jim