Hi,
I am using DAC53608 for voltage margining. Few queries:
1. what's the meaning of "start in a power down to 10k state"? does it mean after VDD ramps up and before write commands, the DAC output (VOUTA-VOUTH) is high-z, while internally it pulls down to GND through 10k? if not, what's the VOUTA-H voltage by default under "power down to 10k mode"?
2. if write the power up command, will OUTA-OUTH output any voltage by default? at this moment, the 10k pull-down is disconnected, right?
3. if the 10k pull down impact the voltage margin calculation? eg. R3, VDAC, etc.
4. could you provide the detailed procedure to implement v-margin? in my application, DAC will be powered up by a standby supply, while the power regulator powers up later.
Thanks.