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ADS8912B: Need information on ADC as SPI Master

Part Number: ADS8912B
Other Parts Discussed in Thread: 66AK2G12

We are planning to use this ADC ADS8912B as a SPI master, for automating the data collection in to RAM without disturbing the processor. But there is no much information available in the datasheet to use this device as a SPI master. In datasheet it is mentioned that the device has to be a slave initially for configuration and then this device can act as a master. This master and slave modes use two different pins as SPI clocks. How do we connect these pins to support this master & slave at the wish of the processor ? Can you point to me to some reference design where this design has been used as a SPI master ?

Thank you,
Sivakumar.

  • Hello Sivakumar,

    The ADS8912B can only generate the data clock synchronized to the data.  The host MCU must still control the SPI bus, including the timing of the /CS and CONVST signals.  The ADS8912B cannot act as a SPI master and talk to external memory.

    There is an application note that discusses the intended use of the ADC-Clock-Master (source-synchronous) mode of operation:

    https://www.ti.com/lit/an/sbaa249/sbaa249.pdf

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Hi Nicholas,

         Thank you for your reply.

         We are planning to use 66AK2G12 processor, we will configure the SPI interface of processor in slave mode.
         This ADC doesn't have to directly store the data into RAM.
         We will use the Timer or PWM signals of the processor to generate the CONVST and /CS.
         When this ADC can pump the data out the SPI of the processor which is configured as slave will receive the data and intimate DMA.
         The DMA will take the data and transfer it to the RAM.
         Is this possible to achieve/implement ?
         If not, what are the other ADC devices that supports this feature ?
         Or is there a way to configure the processor SPI in master mode and read the ADC data thru DMA without the processor getting involved except the initial config ?

    Thank you in advance.

    regards,
    Sivakumar

  • Hello Sivakumar,

    I think what you suggest should work, as long as the DSP generates the CONVST and /CS signals using PWM or timer.

    You will be using Source-Synchronous mode with Internal Clock.  In order to support 500ksps, you will want to use the INTCLK option (15nS serial clock period output on the RVS pin), and you will need to time the CONVST and /CS signals to meet the Zone 1 data retrieval requirements.

    Please refer to figures 5, 44, and 74 in the ADS8912B datasheet for more details.

    The 66AK2G12 may have some limitations on how it is used in SPI Slave mode; you may want to start a new thread in that E2E support forum for specific questions on that device.

    Regards,
    Keith

  • Hi Keith,

         Thank you for the inputs.
         I have few more followup questions on the proposal.

         1. Can the ADC be configured in internal clock mode up on power on ? If processor need to configure the ADC after power on, then how does the clock (RVS) routed back to the processor ? I don't see any strobe pin on the processor for SPI interface in 66AK2G12.


         2. Is there a link between the internal clock and sampling rate of the ADC ? why should we configure the INTCLK to 15ns (66 MHz) to operate the ADC at 500ksps ? If we want 500ksps, 500k x 24 bits = 12Mbps. So if i operate the SPI interface at 12 MHz or little more considering the overhead, it should be fine i guess. This requires the INTCLK should be configured to 60ns (16.5 MHz), so with this setting can i achieve 500ksps ?

         3. The datasheet of this device says that it supports 3-Wire interface as well, where the /CS and CONVST should be shorted together. In this case the /CS will be toggling during quiet acquisition & quiet aperture time, which will affect the signal performance. Is that right ? 

    Thanks and Regards,
    Sivakumar.

  • Hello Sivakumar,

    1. No, after power-up, or RESET, the device must be configured to the Source-synchronous internal clock mode.  You will need an external MCU/DSP with a SPI in master mode to configure the ADS8912B.  I am not familiar with the 66AK2G12, but most processors use GPIO writes to set the /CS (or strobe) over SPI.

    2. The internal oscillator runs at a fixed frequency independent of sample rate.  In your above example, you are assuming that you have the entire converter period of 2uS(500ksps) to transfer data.  Zone 1 requirements only allow transfer of data during the acquisition phase, as shown in Figure 44 of the datasheet.  Since the conversion phase can take up to 1200nS for the ADS8912B, this leaves 800nS minimum for the acquisition phase.  There are also setup and hold times, as well as quiet periods, that subtract from this available time to transfer data, which will be around 700nS.  In order to transfer 24b, the maximum SCLK period will be around 700nS/24=29nS, which is why I suggested that the 15nS INTCLK option will be required.

    3.  It is true that /CS will be toggling, but the quiet time is more sensitive to the SCLK and SDO pins toggling.  You should be able to get full performance out of the ADS8912B in 3-wire SPI mode with a good board layout similar to the evaluation board.

    Regards,
    Keith

  • Hello Keith,

            Thanks for your reply. Please relate the points to the previous thread.

    1. I was asking this question because if we have to configure the ADC, we need to route the SPI CLK from processor to ADC during configuration and later once the ADC is configured as clock master, we will configure the Processor SPI as slave and route the RVS (CLK) to the SPI CLK pin of processor so that that the data can be latched. Let me know if this would work.
     
    2. Got it. If we are planning to fetch the data in Zone 1, we need to operate the SPI at 33MHz (30ns). But if we fetch the data in Zone 2, then we may not have to operate at 30ns, may be 15ns would work. But there is a note in the datasheet page 34 which says that the Zone 2 is not supported in Internal clock mode. Is there a way to do data transfer in Zone 2 with internal clock ?

    3. Are there any other ADCs in TI portfolio to support SPI master functionality in order to reduce the processor overhead.

    Thanks in advance.

    Regards,
    Sivakumar.

  • Hello Sivakumar,

    1.  Yes, your Processor will need a master SPI interface to talk to the ADS8912B using /CS, SCLK, and SDI,SDO.  Once you have the ADS8912B re-configured, you can use the RVS pin as the SCLK input to your processor operating in SPI slave mode.  Please note that the RVS pin always functions as a digital output, and cannot be connected to the SCLK pin since you need to drive SCLK from your processor after reset to configure the ADS8912B.

    2.  No, there is no support for Zone 2 when using the source-synchronous internal clock mode.  You can use a slower clock if you use dual/quad bus width options (requires additional IO pins and the processor may not support), or use the double data rate mode of operation (data are clocked out on both edges of the serial clock(RVS) pin).

    3.  TI has other ADC's with the same/similar interface as ADS8912B, but these all have the same limitations.  I am not aware of any ADC's that can operate in a full SPI master mode of operation.

    Regards,
    Keith