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AMC1306M25: How to design the digital output resistor

Part Number: AMC1306M25

Hi Experts:

I have one question regarding the resistor on the digital output , my customer add the resistor in series in the CLK and DOUT trace and found the value of the resistor

have big impact on the data reading.

If they used the 0ohm or the 100ohm, the reading data will be wrong in sometimes , If they change to the 30ohm , the issue could be fixed.

So my question is how to design the resistor ? what's the best value ?

  • Hi Jason,

    This is not necessarily a simple question to answer without significantly more detail on the PCB construction and the device being used for the digital filtering of the AMC1306M25.  What more can you tell us?

  • Hi  Tim,

    Thanks for your reply ,for the PCB information , i am still inquiring with customer . They used SINC3 for the digital filter. 

    Today , customer capture the data and clock signal between the FPGA and AMC1306 ,like below:

    It seems that the rising and falling edge is slow , might incorrectly trigger the data in sometimes .

    Did it affected by the resistor of the impedance matching ? how to tune it ?

  • Hi Jason,

    The AMC1306 changes data with the rising MCLK edge, so valid data would be read into the SINC3 filter on the FPGA on the falling MCLK edge.  By my rough guess looking at the screen shot you sent, they have ~20 ns setup time and 25/30 ns hold time.  I don't see why this would be an issue in their system.  The only thing I can think of that would cause problems is if they were trying to read data on the rising MCLK edge.