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TLA2518: Achieving full throughput with >13.5MHz SPI, Max Conversion Time, tconv = 600ns, and Datasheet Missing Min. Max. Performance Specs

Part Number: TLA2518
Other Parts Discussed in Thread: ADS7028, ADS7038, ADS7038-Q1, ADS9110, ADS8900B

Hello TI Experts,

Could you clarify some points for me regarding the TLA2518 datasheet?

  1. On the first page of the datasheet, there's a statement "Achieve full throughput with > 13.5MHz SPI".

    1. How is that achievable?

    2. The datasheet gives a spec for the max. conversion time = 600ns, but does not give a min. spec.

    3. From my understanding, to achieve a cycle time of 1us for 1000ksps sampling, if the conversion time is 600ns, I would need a SPI frequency of 60MHz to get a 400ns acquisition time, tACQ, with 24 clock cycles using manual conversion mode.

      tCYCYLE = tACQ + tCONV = 400ns + 600ns = 1us for 1000ksps.

      If I used on-the-fly or auto-sequence mode, with 12 clock cycles, the SPI could be reduced to 30MHz. Is my understanding correct?

    4. Could I use a shorter conversion time (shorter time between nCS high to low) than 600ns to reduce my required SPI frequency for the same throughput?

      There is also a min nCS high pulse duration spec, tWH_CSZ of 200ns, so it's a little bit confusing.

      It would be good for me to be able to use an SPI frequency < 60MHz as I'll be interfacing the ADC with an FPGA and it would make timing closure easier if I could use slower SPI frequencies.

  2. Is the acquisition time, tACQ, dependent on the SPI frequency?

    1. It looks like it from the timing waveforms, but since conversion uses an internal oscillator, are tCONV, tACQ and tCYCLE actually independent from the SPI frequency / clock edges?

    2. If I wanted to achieve say, 500ksps, assuming tCONV = 600ns, in manual conversion mode with 24 clock cycles, I'd need an SPI frequency of 17.14MHz. Would I need to adjust the internal oscillator OPMODE_CFG register so it matches the 500ksps, or could I just leave it at 1Msps?

    3. I guess my question is what is the relationship between the internal oscillator and my SPI frequency? Are they pretty much independent?

      For example, the ADC samples and holds (acquires analog signal) and converts at a rate based on the internal oscillator and my actual data rate is dependent on my SPI frequency, so the device could acquire and convert at 1Msps, but if I use a slow SPI, the actual data rate I get could be 500ksps?

      Could I just leave the internal oscillator running at 1000ksps and use any SPI frequency (acknowledging that my data rate would be less than 1000ksps and I would be missing samples if I use a slower SPI frequency)? What would be the purpose of reducing the internal oscillator frequency then? Just to reduce power consumption?

      Or do I always need to match the internal oscillator and the SPI frequency for the system to function correctly?

  3. If I only need 3 channels out of the 8 channels, are there any recommendations for how to connect the unused channels? Should I connect them to GND or just leave them NC?

  4. I noticed that the TLA2518 seems to be the lowest-end device out of the ADS7028, ADS7038, ADS7038-Q1 family of devices which are pin-compatible.

    1. The TLA2518 datasheet only provides typ. properties for DC and AC performance specs while the ADS7038 datasheet provides min. and max. specs as well.

      Can min and max specs also be provided for the TLA2518?

    2. Could I expect the min. max. specs to be similar to the ADS7038?

Thanks a lot for your help!

Best Regards,

  • Hello Udell,

    This are a lot of questions at once, but I will try to address them all.

    1. You will need to use On-the-fly mode to achieve full throughput. There is no min spec for conversion time, you should follow the Max spec given for all conversions. Your understanding is completely correct.
      1. A conversion is only initiated by the rising edge of CS, the falling edge does not have any effect on the acquisition nor conversion time. The falling edge only needs to follow the minimum time of 20ns. The conversion phase begins with the rising edge of CS, and will automatically finish after 600ns, that is internally done. Once the conversion time has elapsed, the device automatically enters acquisition phase.
    2. The acquisition time does not relay on the clock frequency. Acquisition time end at the rising edge of CS, and ends 600ns after the rising edge of CS (conversion phase). You should not clock out data until 600ns after CS rising edge, as this can result in incorrect conversion results. The internal oscillator and the SPI clock are independent. The internal oscillator comes more into play when using averaging (or autonomous mode in the other devices).

    3. Unused input channels should be grounded.

    4. You are correct that these devices are in the same family. As you have noticed, this device is the lowest end. One aspect to achieve this is limiting test time, which means that performance is not as extensively tested as the other devices in the family. We cannot state performance outside of the datasheet.


  • Hello Cynthia,

    Thanks for your prompt response. You've answered most of my questions.

    Except how is the max. 1000ksps sampling rate achievable using an SPI clock of 13.5MHz as advertised at the beginning of the datasheet?

    When I try to calculate it out, it doesn't seem to work, unless I'm still not understanding it.

    If I must wait 600ns for the conversion to complete before clocking out data, that only leaves 400ns to clock out 12 bits, which would require a minimum SPI clock of 30MHz to get 1000ksps.

    Is it possible to get full throughput with 13.5MHz or is that an error on the datasheet?

    The datasheet states the device has the TI Enhanced SPI to allow for slower SCLK speeds and I found an app note describing it

    Does this device support the "Enhanced SPI" features described in the app note and that's why it states full throughput with >13.5MHz and Enhanced SPI?

    The TI Enhanced SPI feature doesn't seem to be described in the datasheet and the section only describes standard SPI polarity and phase settings.

    Can the device operate similar to what's described in the ADS892xB datasheet, section 7.5.3, sampling in Zone 2 to use slower SCLK

    Thanks again,


  • Hi Udell,

    You are right, the lower speed SPI interface with 1Msps sampling rate is possible with zone 2 data transfer. However, the minimum CS high time is 200ns in the active datasheet (it was 30ns in the preview datasheet). With 200ns CS high time, the host would have 800ns to read the 12-bit conversion result. Hence 1Msps sampling rate is achievable with 15MHz interface clock.

    I have made a note to update the "13.5MHz" spec on the front page of the datasheet. Thanks for sharing your feedback.

  • Thanks Rahul,

    That answers my question.

    It would be helpful to add more detailed timing information in the datasheet as well, regarding clocking out data after the 200ns CS high time to be able to reduce SPI clock speed.

    Cynthia had mentioned that, if I clock out data before the 600ns conversion time, there could be conversion errors?

    This seems to conflict with being able to clock out data after 200ns. Is this true?

    Or as long as I don't toggle any signals within the +/-10ns quiet conversion and quiet acquisition times before and after the rising edge of CS, then it should be fine?

    Best Regards,


  • Hi Udell,

    In the TLA2518, there is only one ground pin for the chip. Hence when reading data during an ongoing conversion can result in reduction in SINAD in TLA2518.

    This is not a limitation for the other devices mentioned in the app note. This is because devices like ADS8900B, ADS9110, etc. have multiple ground pins.



  • Hi Rahul,

    Thanks for answering all of my questions. It helps a lot.

    Best Regards,