This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AFE58JD18: Active termination during power down

Part Number: AFE58JD18

When using active termination and powering down the voltage on the Cact input is 1.7V. Without this active termination it is 1.5V.

During the power down the Cact is charged to the 1.7V, after returning from power down this charge is then coupled to the input
resulting in an enormous signal offset.

Have you seen this behaviour before and what can be done to avoid this?

Thanks,

Ed

  • Ed,

    yes. this is expected to power up settling time.  we suggest the below: 

    NOTE
    To achieve a fast wake-up, always ensure that the active termination is disabled while the
    device is in fast power-down. For applications where active termination is desired, disable
    active termination 5 μs before making PDN_FAST/FAST_PDWN = 1. The active
    termination can be re-enabled 5 μs after setting PDN_FAST/FAST_PDWN = 0. This
    sequence ensures optimum wake-up time

    Thanks!