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ADS42LB49: ADS42LB49 Vs ADS5500 SNR

Mahmoud Zannerni62
Intellectual 655 points
Part Number: ADS42LB49
Other Parts Discussed in Thread: ADS5500, , CDCV304, CDCE62002

Hello,

I am performing 512 point FFT on both adcs with sampling rate 100 MHz

ADS5500 using differential clock source 

ADS42LB49 using cmos clock source 

The input signal is about 8 MHz.

The FFT noise floor of the power spectra seems lower in ADS5500, I was expecting the ADS42LB49 to perform better?

Does using lvds clock for ADS42LB49 makes a big difference? what other factors could be affecting the performance of ADS42LB49,

I am using ADS42LB49EVAL and a 3rd party board for ads5500.

 

Regards,

Mahmoud

  • 0
    TI__Guru* 91947 points

    Mahmoud,

    To do a true test, it would be best to use the same clock source for both as clock jitter will effect performance. I would suggest using a clean signal generator connected to J3 of the EVM with transformer T5 providing a differential clock to the ADC. You may also want to add a band pass filter (if available) between the signal generator and the SMA. You should be getting typical data sheet numbers with this board. You will also notice performance improves with high clock amplitude (Figures 27 and 28 of data sheet). Check the amplitude of the clock at the ADC pins.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 655 points

    Thanks Jim,

    Unfortunately, I cannot access the clock pins on the ads5500 board.

    but clock circuit uses regular 100 MHz oscillator with CDCV304 clock buffer and SY100EPT28L to convert TTL to LVPECL.

    I am using CDCE62002 as my clock source for ads42lb49eval, and the clock source is set to 3.3 votls cmos output, but as you mentioned there is on board transformer so the clock is differential.

    I just noticed the transformer has ratio of 4 so the clock voltage is divided by 4? sounds like this is the issue?

    I don't have access to fast scope to check the clock on adc inputs.

    I was using a 3db attenuator between cdce62002 eval and ads42lb49, after removing it the noise floor went down a bit but still worse than ads5500.

    Regards,

    CDCV304

  • 0 in reply to Mahmoud Zannerni62
    TI__Guru* 91947 points

    Mahmoud,

    I think the issue is your clock source. You need to try and find a signal generator to do a comparison test. The transformer will actually amplify the clock not divide it. You may be overdriving the clock. You need to measure the level at the ADC inputs. Use a lower clock frequency if your instrument can only measure a lower frequency. 

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 655 points

    Hi Jim,

    I have checked the output of CDCE62002 and it is 3.6 volts p-p and the same values measured on the ADC clock inputs.

    I am using D2 pads to check with two single ended channels of the scope subtracted (A-B)

    I have added 13 db attenuator and the voltage on ADC side now is 1 V p-p and the SNR is much better!

    What is the ideal value for this voltage? I am not sure which line of the table I should use in the case of having lvcmos clock and transformer to convert it to differential as in the eval.

    Regards,

    Mahmoud

  • 0 in reply to Mahmoud Zannerni62
    TI__Guru* 91947 points

    Mahmoud,

    I would adjust the CMOS output level so that the diff clock input after the transformer is 1.5 V p-p.

    Regards,

    Jim