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DAC38J84: Not using PLL inside DAC . Problem at high Speed. Sync is toggling at High Data Rates

Pavan
Intellectual 730 points

Part Number: DAC38J84
Other Parts Discussed in Thread: LMK04826, , LMK04828

Hi

1.

Sampling rate is 312.5 MSPS 

External DAC_CLK from LMK04826 is 2500 MHz .

Interpolation = x8

Serdes rate = 6.25 Gbps

MODE : 4421

Now what is the value of the SERDES_Clock ?? and what is the difference between JESD Clk, Dac clk and Serdes Clk ??

2. Sampling rate = 312.5Msps , Dac clk = 312.5 MHz Interpolation = x1, serdes rate = 6.25 Gsps, Mode = 4421, sysref =  4.88 MHz

In this case, i am bypassing my DAC PLL, then Sync signal for JESD protocol is working and I am able to see sinewave on CRO., but if I use interpolation

Sampling rate = 312.5Msps , Dac clk = 2500 MHz Interpolation = x8, serdes rate = 6.25 Gsps, Mode = 4421, sysref =  4.88 MHz, then

JESD Sync signal is continuously toggling, So I am not getting proper data.

Is this issue due to bypassing DAC PLL ??

I am using LMK04826. Max output freq is 2500 MHz. I am using the upper limit freq 2500 MHz . Any problem with it??

What is the use of DAC PLL ??

  • 0
    TI__Guru* 81495 points

    Hi,

    pavan kumar8 said:
    Now what is the value of the SERDES_Clock ?? and what is the difference between JESD Clk, Dac clk and Serdes Clk ??

    you may use the DAC38J84 EVM GUI to configure these clocks. These clocks are needed to clock the SerDes block and JESD204 IP inside the device

    pavan kumar8 said:
    Is this issue due to bypassing DAC PLL ??

    No, this is purely due to the JESD204 link. You will need to check the JESD204 IP error and resolve the issue independently.

    pavan kumar8 said:

    I am using LMK04826. Max output freq is 2500 MHz. I am using the upper limit freq 2500 MHz . Any problem with it??

    What is the use of DAC PLL ??

    you will need to check the drive strength of the LMK04826. You may want to use the LMK04828. Please post on the clocking forum for additional question on the LMK04828

    DAC PLL allows you to use lower cost clock device and utilize the internal DAC PLL to create the sample clock. Since you are using LMK04828, you do not need tow worry about this.

    -Kang

  • 0 in reply to Kang Hsia
    Intellectual 730 points

    Hi

    My sampling Rate is 312.5 MSPS. 4421 Mode. x1 Interpolation

    I am giving input of 25 MHz

    So at DAC output spectrum, I am getting peaks at 25 MHz and also at 312.5 - 25 MHz , 312.5 + 25 MHz

    1. I think this is the correct behaviour. Is it correct ??

    2. In the DAC, there was an FIR Filter. Can I use it as a Low Pass Filter to eliminate the Higher Order Harmonics ???  If yes How ??

    3. If my JESD Clk is 312.5 MHz, then what is the value of SERDES_Clk ???

  • 0 in reply to Pavan
    TI__Guru* 81495 points

    Hi,

    1. If your input is real, independent signal, then yes, this is correct behavior. If you inject complex I/Q signal, then it should be single sideband

    2. FIR filter is used in conjunction with upsampling to complete interpolation. It will not filter out higher order harmonics at the DAC output as the DAC output harmonics requires analog filtering (i.e. anti-aliasing filter)

    3. these two clocks are not related completely. You may have JESD clock at 312.5 with different SerDes clock, depending on the SerDes speed

    use the DAC38J84 GUI to determine the setting

    -Kang

  • 0 in reply to Kang Hsia
    Intellectual 730 points

    Hi,

    These two clocks are not related completely. You may have JESD clock at 312.5 with different SerDes clock, depending on the SerDes speed

    use the DAC38J84 GUI to determine the setting.

     

    My SERDES Rate is 6.25 Gbps , DAC _Clk is 2.5 GHZ , Sampling Rate is 312.5 MSPS, x8 Interpolation, then what will be my SERDES Clk Rate??

    In the DAC GUI, it is not showing the Exact value. 

  • 0 in reply to Pavan
    TI__Guru* 81495 points

    Pavan,

    Please see below for example configuration you can generate from the GUI. It gives full rate as an example. You may then use the full-rate to see the SerDes PLL is running at 1x of the SerDes rate.