DAC7760: SPI communication problem with DAC7760

Rameez,

Can you please clarify what you actually read back during the read sequence to help us understand exactly how the communication appears to be failing?

It would also be helpful to see an oscilloscope capture of the SYNC, DIN, SDO, and SCLK lines to verify timing and that the correct clock edge is being used to communicate with the device.

Hi Rameez,

There could be many causes of this.  Please share your schematic as a good start.

In addition, please make sure the SPI timing complies with the SPI timing diagrams. Feel free to share an oscilloscope capture if you are unsure.

Thanks,

Paul

Hi Paul,

I'm sharing a hand drawn schematic of DAC7760. 

Hi Duke,

The output I'm getting is not constant, sometimes it is coming 0x000000 sometimes it is coming as 0xFFFFFF and sometimes it's just random value.

Regards,

Rameez

In the above circuit i have  boost pin open. When i power the DAC the boost pin output gives 15V. Is there any issue with it.

Hi Rameez,

Boost should be equal to AVDD if there is no current on IOUT.

I recommend you capture the SPI transaction and verify the edge timing.  In addition, you verify the device is correctly connected, especially if this is a hand-wired PCB. 

Hi Paul,

Thanks for ur reply I have resolved my communication problem, there was a connection issue. Now I'm facing new problem I'm able to read only DAC Data Reg  and can't read another registers. 

I'm writing (0x01,0xFFFF) to get full scale voltage, and I'm reading at (0x02,0x0001) it's equivalent code i.e 0xFFE. 

But when I'm writing control reg (0x55,0x1001) and reading the same reg (0x02,0x0002) I'm getting 0x000000 at output.

Regards,

Rameez

A few things:

1. Confirm with a scope that the bus is actually reading 0x0FFE rather than 0x0FFF.  If your clock phase is incorrect, the MCU might be incorrectly reading the data.

2. You are using the DAC7760, so it is 12-bit.  The most significant 4 bits are ignored, so when you wrote 0x1001, the device would latch 0x001.  

Thanks, 

So now help me in writing and reading the registers for DAC 7760 as it 12 bit.

You are telling that out of 16 bits only 12 bits are latched and most significant 4 bits are ignored. 

But in datasheet below table 18 it says least significant 4 bits are ignored.

So how to configure the registers for 12 bits and which bits should be ignored.

Hi Rameez,

You are correct, I miss read the table.  Bits D3:0 would be ignored. 

I am not confident the data is being latched correctly.  I recommend you try a few different values to see if we can detect a pattern.

Try these values and measure the result.  If the value is incorrect, you might try changing the phase/polarity of the SPI clock or verify it's correctness with a scope.

0xFFF0

0x8000

0x7FFF

0x1000

0x0FFF

Let me know the results.

Thanks,

Paul

Hi Paul,

I tried giving different inputs like 0xFFF0, 0x7FF0 and 0xAAA etc. For data  0xFFF0, 0x7FF0 the output I'm getting is  0xFFE0, 0x7FE0 but for 0xAAA0 I'm getting 0x8000. I'm attaching scope images for ur reference. 

I also tried changing clock polarity/phase but it doesn't seem to work.

Hi,

I have few questions:

Are control & configure registers R/W or only W?

I'm able to write to these registers but can't read them.

Only DAC Data Reg can be read.

What should be the exact problem for this.

I have attached waveform for SCLK & SDI/SDO,

1st is Reading Control Register.

2nd is Writing Control Register.

3rd is Writing DAC Data Reg.

4th is Reading DAC Data Reg.

Hi Rameez,

The configuration register is readable, but the data is clocked out in the next command.

So if you want to read the configuration register, you issue the following commands:

1. 0x020002 //this set the config register as the next read

2. 0x000000 // this is the NOP command that must immediately follow.  I do not recommend using the next write command in your case.  

Lets make sure that the config and DAC register are reading back correctly.

Hi,

I'm following the same steps as suggested but still no luck with reading the control reg.

Thanks,

Rameez

Why 1 bit is shifted at the receiving end.

If i send 0x0F i'm getting 0x07.