ADS4126: Timing of CMOS outputs

David Wende

Part Number: ADS4126

We are clocking this part at 150MHz with low latency mode and then sampling the CMOS output in an FPGA.

Sample clock is the ADS4126 input clock (i.e. not using CLKOUT).

I am trying to understand the time at which data will be valid relative to the rising edge of input clock.

Q1: In table 5 and taking 170MHz as example, is 1.5nS before the clock rising edge the EARLIEST or the LATEST time the data becomes valid?

We are extrapolating to 150MHz from the timing values in table 5 and using Tstart = -2.2nS and Tdv = 4.7/5.5.

Q2: Is this a valid approach?

Q3: If so, is rising edge-2.2 the earliest or the latest time that data becomes valid?

Thanks for any help.

over 5 years ago

0 David Chaparro over 5 years ago

TI__Mastermind 18001 points

Hi David,

We are looking into this and will let you know what we find.

Regards,

David C

0 jim s over 5 years ago in reply to David Chaparro

TI__Guru* 91947 points

David,

Q1: In table 5 and taking 170MHz as example, is 1.5nS before the clock rising edge the EARLIEST or the LATEST time the data becomes valid?

This is the earliest data is valid.

We are extrapolating to 150MHz from the timing values in table 5 and using Tstart = -2.2nS and Tdv = 4.7/5.5.

Q2: Is this a valid approach?

Since there are no measured values for 150MHz, this is not guaranteed. To be on the safe side I would suggest using the timing numbers for 170MHz.

Q3: If so, is rising edge-2.2 the earliest or the latest time that data becomes valid?

Based on the 170MHz numbers, data will be valid no latter than -1.5 ns before the rising edge of the input clock and will be valid at least 4.7 ns after the rising edge when using a 150MHz clock.

Regards,

Jim

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ADS4126: Timing of CMOS outputs