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ADS1220: Crosstalk on ADS1220

Silvano Ghilardi
Intellectual 330 points
Part Number: ADS1220

Hi

I'm using the ADS1220 and I measure two DC voltages. U1 from AIN0 to AIN1 and the second U2 from AIN2 to AIN3.

So if I make a step with U2 around 0.6V I can see a step, calculated back of around 200uV on U1. I have got the some circuit one revision of the board before and it was not there.

What could be the reason?

Thanks for the help.

BR

Silvano

  • 0
    TI__Guru** 112635 points

    Hi Silvano,

    What was changed between revisions?  That would be the first place to start looking.

    Can you send me the schematic and board layout?  Also it would be helpful to know the register settings being used and in particular the PGA settings and the data rates used.

    If you have a step change and it affects a different input on a different IC, then most likely there are traces that are running close together or perhaps change layers near the other input traces.  Also, the PCB ground should be a solid ground.  If the ground is interrupted the return path of the signal will not be optimal and may run past the other input unintentionally.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Intellectual 330 points

    Hi Bob

    Thanks for the fast replay. 

    I have two output ports which are powered from two OpAmps. These outputs are measured by one ADS1220. The main change was to replacement and repositioning these two OpAmps.

    So if I make a step on one output from around 0V to 6V to other ADC path measures a step around 200uV on his own output. I have made several measurements and I could exclude everthing around ADC. In the end I found out, that when I short the second input of the ADC directly at the input pins, the step is gone. But if I keep the resistor for the filter (6.8kOhm) and make the short connection in the front of this resistor, then I see the step. So I supposed it has to be related to any kind of input current of the ADC. I have checked the datasheet of the ADS1220 and found figure 16. Could this current by the problem?

    Please check the schematic and the print screens of the layout.

    Thanks 

    BR

    Silvano Schema.docx

  • 0 in reply to Silvano Ghilardi
    TI__Guru** 112635 points

    Hi Silvano,

    Absolute input current alone through the 6.8k resistor would not account for a 200uV jump.  Could you send me the register settings that you are using?  Just so that I'm clear, in the first post you said 0.6V step but in the second post you mentioned a step of 0 to 6V.  6V would be outside of the input range of the ADS1220.  If the step is 6V then you would be running excess current inside of the device which will affect the measurement of other channels.

    Also it is not clear what I'm actually seeing in the layout plot.  Actual gerbers would be much easier to follow.  How many layers is the PCB and what is on each layer?  Also, it appears that the connections to the analog inputs do not match with the schematic.  The inputs that connect to GND also appear to connect to a different component.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Intellectual 330 points

    Hi Bob

    Sorry these explanations were unclear. 

    Condition: If I do a step around 6V at Pin 6 of U32, I will have a step around 0.6V at AIN2 of U26. This step will cause a step, shown in the output data of U26 (ADS1220), around 200uV at Pin 6 of U31 or around 20uV at AIN0 of U26. I can't measure these voltage levels (20uV and 200uV). I only see the output data of U26 (ADS1220).

    If I calculate the voltage drop over R32 (6.8kOhm) with the possible current out of AIN0, it could be around 20uV. Sorry this is the point that I mean. 

    To the setting. I don't have the registers available now, but I know the settings.

    - Gain = 1; PGA = on; Ref = ext 2.5V; Mode = normal, DataRate = 175sps

     

    I have also made some additional measurements and I have seen that when I reduced the R32 and R33 to 330Ohm and increase C129 and C130 to 10uF, it looks like, that I can solve this issue and keep the filter frequency. 

    However, I'm not sure if I understood this issue right and if this solution is correct. In the end, it looks like an input filter issue for me. Perhaps you can also tell me a guideline for the input filter design.

    Thanks

    BR

    Silvano

    5305.PCB.zip

  • 0 in reply to Silvano Ghilardi
    TI__Guru** 112635 points

    Hi Silvano,

    You labeled this thread as crosstalk, but I think the real issue is analog settling at the inputs.  As you are using very heavy analog filtering, there is a significant time constant.  What you may be seeing is a result of settling.  I presume that the voltage will settle out at some point.  

    The input currents are a result of two areas.  One is the input sampling current and the other is leakage current.  The input bias current from sampling should be quite small with respect to having the PGA enabled.  Leakage current will not start to dominate until the ADS1220 reaches high temperature operation where diodes, transistors and switches become leaky.  

    So there is some input bias current always due to sampling, but then you would always see this error when using larger values of resistors.  As you see a significant conversion result change during a step input, then this would reflect on the ability of the charge to be delivered to the ADC input quickly enough to allow for a stable input voltage.  This becomes an analog settling issue at the input as current drawn from sampling moves from the filter cap to the input sampling circuitry and then must be replenished through the filter resistance.  This effect will only get worse if the PGA is disabled and bypassed, so I would verify that the register setting is actually showing that the PGA is enabled and your configuration is actually setting the register bit to 0 for bit 0 in configuration register 0.

    You may question why the same filter cutoff has differing responses.  First, the charge moves slowly through the larger value of resistor and will also create a voltage drop across the resistance.  As the cap value is also small, the movement of charge to/from the capacitor from the input sampling stage is much quicker than the ability to restore charge from the input.  Charge from the sampling of one input can actually move to the filter cap of the next input channel to be measured in certain conditions. With the smaller filter resistor the input voltage charge moves more quickly to the filter cap and the large value of filter cap will act as a charge reservoir to the analog input sampling stage.

    As I stated previously, the input sampling and movement of charge is much different with respect to whether the PGA is enabled or disabled.  Also, using larger values of resistance will affect the measurement with respect to error due to any voltage drop across the input resistor.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Intellectual 330 points

    Hi Bob

    Ok, thanks for the help. In the end, I can do several things.

    1. Reduce the input resistors to speed up the charge/discharge of the input capacitors

    2. Increase the input capacitors to have a better buffering (during charging/discharging of the sample circuit)

    3. Keep the PGA enabled (in any case)

     

    I will double check this heavy input filter. Perhaps we can change it.

     

    Thanks for the help.

    BR

    Silvano