Other Parts Discussed in Thread: AMC1306E25, AMC1306M05, , AMC1306E05
I want to understand what bit pattern to detect on DOUT for the failure scenarios below.
In the datasheet for AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25 SBAS734A –MARCH 2017–REVISED JULY 2017 section 8.4.1 describes in words that the output DOUT of the device offers a steady-state bitstream of logic 0's in case of a missing AVDD. It also describes if the common-mode voltage of the input reaches or exceeds the specified common-mode overvoltage detection level VCMov then a steady-state bitstream of logic 1's are output on DOUT. However, Figure 53 appears to suggest that a Test Pattern exists when AVDD is good. From the wording above I do not expect that pattern to be anything other than 1's, is that correct.
Also I don't know whether there is a way of knowing through DOUT when t ASTART starts which would be required as that determines when DOUT has a Valid Bit Stream.
What I intend to do is monitor for 128 or more consecutive 0's or 128 or more consecutive 1's and if either of these are detected then the Bit Stream in not Valid. To transition to a Valid Bit Stream requires DOUT to not have 128 consecutive '0's or not have 128 consecutive 1's. Is that the correct assumption?