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ADS8167: influence on other channels when using MUX

Part Number: ADS8167
Other Parts Discussed in Thread: OPA320

Hi,

I'm currently evaluating a design around ADS8167 ADC. The schematic is more or less equal to Figure 107 in the datasheet. Whenever I'm reading a single channel (mux is selecting channel constant) the voltage reading is very accurate. Once I start using the device in sequence mode, I am seeing an influcene from the previous ADC channel to the current one. So if CH0 voltage is higher compared to CH1, a positive error is added to CH1 reading. If CH0 voltage is lower compared to CH1, a negative error is added to CH1 reading.

Sequence is triggered @ 1kHz, conversion result readout is done after "READY" flag is set by ADS8167.

Can this be caused by a wrong access to the ADC or is it more likely caused by hardware issue (RFLT/CFLT)?

Should i try to bypass the buffer and connect muxout directly to adc-in?

Many thanks for your help!

BR Benjamin

  • Hello Benjamin,

    Welcome to the TI E2E community.

    The circuit in Figure 107 should easily settle, assuming you are using the OPA320 amplifier and the same RFLT/CFLT values.  (There is a typo for CFLT, it should be 1.2nF, not 1.2uF.)

    This is likely a settling issue, and could be caused by incorrect RFLT/CFLT values, or using a very low bandwidth amplifier instead of the OPA320.  Also, the 'settling' could show up due to an incorrect value for reference cap (20uF nominal).

    Please send a screen shot of your schematic showing the exact values and amplifier used similar to Figure 107 and I will review.

    Also, I assume you are sampling at 1kHz (frequency of /CS pin).  In this case, you probably do not need the OPA320 buffer, so you could try bypassing this amplifier and see if this helps settling during scanning.

    Thanks!

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • Hi Keith,

    thank you for your quick reply!

    My circuit is equal in terms of selected devices (so OPA320 as buffer) and values to Figure 107. The only differences are the external 5V reference which supplies both REFIO/AVDD and the input lowpass on each individual input where I'm using 133k/10nF(X7R).

    About sampling - I'm starting the sequence every 1ms and read one sample, once the previous conversion is done (see code snippet below)

    void tick_1ms()
    {
    
    	ads8167SetBits(REG_SEQ_START, (1 << CFG_SEQ_START)); //Start sequence
    	ads8167ConversionBusyWait(); //Wait for first conversion to finish
    	ads8167ReadFromSequence(); //Skip initial sample
    	
    	for(uint8_t i = 0; i < 8; i++)
    	{
    		ads8167ConversionBusyWait(); 
    		analogValues[i] = ads8167ReadFromSequence();		
    	}	
    	
    }
    
    uint16_t ads8167ReadFromSequence()
    {
    	uint16_t convResult;
    	ads8167Select();
    	convResult = (spiTx(0xff) << 8) | spiTx(0xff);
    	ads8167Deselect();
    	return convResult;
    }
    
    void ads8167ConversionBusyWait()
    {
    	while(!(ADS8167_READY_INPUTPIN & (1 << ADS8167_READY_PIN)));
    }
    

    I will try to bypass the buffer & see if this helps with the issue.

    Many thanks!

    BR Benjamin

  • Hi Benjamin,

    There is a parasitic capacitance on the output of the multiplexor that consists of the multiplexor switches, as well as the input capacitance of the OPA320, and the board.  If CH7 is charged up to the full scale voltage of 5V, and then you switch to CH0 with an input of 0V, there will still be a settling time required to charge up this capacitance.  Your input filter is much too slow in this case for a 1mS update rate.

    I did a quick calculation, and using a 10nF capacitor on each of the input channels, the maximum resistance will be 18.9kohm.  Try reducing your input resistor values from 133kohm to 18.9k or less and see if this fixes your settling issues.  If you speed up your sample rate, for example sample at 100uS, then the input filter time constant will need to be further reduced.

    Thanks,
    Keith

  • Hi Keith,

    thank you for your great support!

    The slow rc filters on the inputs were designed to have a low enough cutoff frequency for the 1kHz sampling rate in order to minimize aliasing. If I calculate with your suggested values I would end up with around 840Hz versus 119Hz from the original design.

    Is there a possibility to maintain the low cutoff frequency in combination with 1kHz sampling rate and reduce the settling time? I suppose the input capacitor could be increased from 10nF to help getting the the paracitic capacitance charged?

    Thanks,

    Benjamin

  • Hello Benjamin,

    If you need to support 1ksps scanning rate, and you want to use a filter with 119Hz cutoff, then the only option would be to increase the input cap as you suggest.

    Keep in mind that the total error in one channel near full scale, and the next channel near 0V, will depend on the ratio of the mux output capacitance (estimated to be 15pF) and the input cap.  Increasing the capacitor to 100nF, and decreasing the input resistor to 13.3kohm to the same cutoff will result in a worst case settling error of about 380uV, or 5LSB's.

    Regards,
    Keith

  • Hi Keith,

    after changing the input filter to 100nF/10k the settling issue is within the range you have mentioned. For this application it is more than enough. Just for my interest, to get true 16bit readings a slower ADC would be better in this case? So it would allow for longer settling time?

    Thank you again for your help, much appreciated!

    Regards,

    Benjamin

  • Hi Benjamin,

    Glad that this is now working for your application.

    The settling time really has nothing to do with the ADC function; it is entirely due to the integrated multiplexor switches.  You would see the exact same issue with a discrete multiplexor IC as well.

    Since you are using a single ADC core to multiplex between multiple channels, it must run at a faster rate to support each individual channel; ADC is running at 1ksps, and each of the 8 channels is sampling each input at 1k/8=126sps.

    The other option is to use an individual buffer on each of the inputs, as shown in Figure 100 of the datasheet.  In this case, the amplifier drives the output multiplexor capacitance, plus the ADC inputs.  You can then use a much wider range of input filter values, including 133kohm and 10nF.  However, the tradeoff is that you need 8 amplifiers, instead of a single amplifier as you are now using.

    Regards,
    Keith