Other Parts Discussed in Thread: OPA320
I'm currently evaluating a design around ADS8167 ADC. The schematic is more or less equal to Figure 107 in the datasheet. Whenever I'm reading a single channel (mux is selecting channel constant) the voltage reading is very accurate. Once I start using the device in sequence mode, I am seeing an influcene from the previous ADC channel to the current one. So if CH0 voltage is higher compared to CH1, a positive error is added to CH1 reading. If CH0 voltage is lower compared to CH1, a negative error is added to CH1 reading.
Sequence is triggered @ 1kHz, conversion result readout is done after "READY" flag is set by ADS8167.
Can this be caused by a wrong access to the ADC or is it more likely caused by hardware issue (RFLT/CFLT)?
Should i try to bypass the buffer and connect muxout directly to adc-in?
Many thanks for your help!