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ADS1115: Input capacitor stage of ADC

DARSHAN salian
Prodigy 100 points
Part Number: ADS1115

I was reading the datasheet of ADS1115. It has an input capacitor stage which it continuously charges and discharges to measure the voltage between AINp and AINn.

  1. It is written in the datasheet that the capacitor used in the input stage are small and to external circuitry, the average loading is resistive. How it can be resistive?
  2. Once the capacitor is charged and S1 is closed and S2 is opened, it discharges to 0.7V. Why does the capacitor discharge to 0.7V?
  • 0
    TI__Guru* 97945 points

    Darshan,


    The input is modeled as an impedance because of the periodic sampling and discharge of the input capacitance. As charge is periodically carried away from the input, this appears as an amount of charge leaving the input over time that varies with the input voltage.

    Starting with capacitance (C), it comes from charge (Q) divided by the voltage (V).

    C = Q / V

    This leads to: V = Q / C

    If the charge is sampled and discharged periodically over a time (t), then you can apply this to the previous equation:

    V = (Q/t) / (C/t)

    Now because Q/t is the equivalent input current (I) of the sampling capacitance, you can rewrite this as:

    V = I / (C/t)

    This can then be rewritten with V/I which is the equivalent resistance R:

    V/I = R = t/C

    The ADC is a delta-sigma type ADC with an integrator as part of the modulator. The input is sampled into integrator in the modulator. The charge and discharge point of the input sampling capacitance is a 0.7V node in the ADC.


    Joseph Wu