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DAC60004: Data converters forum

ttd
Mastermind 7670 points
Part Number: DAC60004

Dear Technical Support Team,

I'd like to replace from AD5024 to DAC60004.

I have been facing the command hung issue with AD5024.
AD5024 doesn't accpept the command trough SPI on the system.Output level of AD5024 keeps the last command of data andit doesn't change the output level when FPGA send command.

The only improvement is when the power is turned off

I don't know the route cause currently. However If I replace from AD5024 to DAC60004, I hope to resolve this issue.
If you have any information about noise immunity about SPI Interface, could you share it?

Or , for example, when undefined input(such as more pulse, more clock etc) on datasheet is applied in SCLK / SDIN / SYNC ,
Does it work without hanging? If SPI hangs and DAC60004 doesn't accept command, then I hope SPI works again with POR pin or CLR pin.

I really hope to replace from AD5024 to DAC60004 to avoid command hung issue.

I think that you can't mention "No problem" , unless I find the route cause of the current problem.
but if you have any information, please give me some advice.

Best Regards,

ttd

  • 0
    TI__Mastermind 18546 points

    Hi,

    I cant comment anything on AD5024.

    For DAC60004, I can explain.

    SCLK :  we need min 32 SCLK for Data update, if its more than the specified clocks, device will take the last 32 clock pulse and corresponding SDI data 

    SYNC : For stand-alone operation, the SYNC line stays low for at least 32 falling edges of SCLK and the addressed DAC register updates on the 32nd SCLK falling edge. However, if SYNC is brought high before the 32nd SCLK falling edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs.

    SDIN :  Data should be in sync with SCLK as I mentioned earlier, if its less than 32 SCLK, data will be discarded.

    Hope this clarifies your queries.

    Regards,

    AK

  • 0 in reply to Akhilesh K
    Mastermind 7670 points

    Hi AK,

    Thank you for your reply.

    How about the case of the next normal communication when the SCLK becomes a double clock and the address/data becomes invalid?

    The CLK is at least 32 CLK, but when 33CLK is applied, if the first 32 CLK is reached, double clock generation will cause incorrect data to be written.

    Best Regards,

    ttd

  • 0 in reply to ttd
    TI__Mastermind 18546 points

    Hi ttd,

    If you are starting next SPI frame with SYNC High to Low transition, Data will be valid. Otherwise, data will be invalid.

    Regards,

    AK