When the value of sync_fifo(2:0) of SYNC_CNTL register (Address 0x05) is set to 010 and the interleave bus mode QFLAG is set,
Is it okay to open the TXENABLE pin?
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
While having the QFLAG set for the interleaved bus mode you will need the TXENABLE pin to be pulled high so that your data is enabled to the DAC. The TXENABLE pin has an internal pull down resistor, so we recommend using a 10 kOhm resistor to 3.3V to pull it high.