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ADC32RF45: JESD Sync Loss

Part Number: ADC32RF45

Hi,

We're currently having a problem where we lose SYNC between the ADC32RF45 and the JESD204 core in our Xilinx FPGA.

After initialization of the ADC the following is received on the output of the Xilinx JESD core.  We appear to lose sync multiple times until all we receive is "BCBC" on the JESD lanes.

Upon resetting the JESD cores we get the following:

Note that the duration of rx_tvalid is not always the same.

When we review the Xilinx JESD204 cores registers, the Link Error Status register indicates that every lane received unexpected K-character(s).

Does anyone have any insight as to why this would be happening?

Thank you,

DT

  • Hi DT,

    Can you please provide details on ADC32RF45 mode that  you are trying to use? What are the JESD mode (LMFS), ADC clock speed, DCC/ bypass mode and DDC factor? 

    Link parameters configured on FPGA should match programmed ADC mode for JESD sync to establish.

    Regards,

    Vijay

  • Hi Vijay,

    We have the ADC set for LMFS = 82820, ADC clock speed of 1500 MHz, and bypass mode.

    FPGA is configured with the following: Line rate = 6 Gbps, Ref clock = 150 MHz, L = 8, F = 8 and K = 16.

    Thanks,

    DT

  • Hi DT,

    Can you please send the ADC32RF45 config file you are using? Have you verified it on an ADC32RF45EVM? 

    Regards,

    Vijay

  • Hi Vijay,

    Unfortunately we don't have the ADC32RF45EVM.

    We based our register writes from the config file from the ADC32RFxx EVM GUI.

    adc32rf45_lmfs_82820_config.txt
    writeAdcReg(0x0000, 0x81); // Global software reset
    writeAdcReg(0x0011, 0xFF); // Select ADC page
    writeAdcReg(0x0022, 0xC0); // Analog trims start here
    writeAdcReg(0x0032, 0x80);
    writeAdcReg(0x0033, 0x08);
    writeAdcReg(0x0042, 0x03);
    writeAdcReg(0x0043, 0x03);
    writeAdcReg(0x0045, 0x58);
    writeAdcReg(0x0046, 0xC4);
    writeAdcReg(0x0047, 0x01);
    writeAdcReg(0x0053, 0x01);
    writeAdcReg(0x0054, 0x08);
    writeAdcReg(0x0064, 0x05);
    writeAdcReg(0x0072, 0x84);
    writeAdcReg(0x008C, 0x80);
    writeAdcReg(0x0097, 0x80);
    writeAdcReg(0x00F0, 0x38);
    writeAdcReg(0x00F1, 0xBF); // Analog trim ends here
    writeAdcReg(0x0011, 0x00); // Deselect ADC page
    writeAdcReg(0x0012, 0x04); // Select Master page
    writeAdcReg(0x0025, 0x01); // Global analog trims start here
    writeAdcReg(0x0026, 0x40);
    writeAdcReg(0x0027, 0x80);
    writeAdcReg(0x0029, 0x40);
    writeAdcReg(0x002A, 0x80);
    writeAdcReg(0x002C, 0x40);
    writeAdcReg(0x002D, 0x80);
    writeAdcReg(0x002F, 0x40);
    writeAdcReg(0x0034, 0x01);
    writeAdcReg(0x003F, 0x01);
    writeAdcReg(0x0039, 0x50);
    writeAdcReg(0x003B, 0x28);
    writeAdcReg(0x0040, 0x80);
    writeAdcReg(0x0042, 0x40);
    writeAdcReg(0x0043, 0x80);
    writeAdcReg(0x0045, 0x40);
    writeAdcReg(0x0046, 0x80);
    writeAdcReg(0x0048, 0x40);
    writeAdcReg(0x0049, 0x80);
    writeAdcReg(0x004B, 0x40);
    writeAdcReg(0x0053, 0x60);
    writeAdcReg(0x0059, 0x02);
    writeAdcReg(0x005B, 0x08);
    writeAdcReg(0x005C, 0x07); // Global analog trims end here
    writeAdcReg(0x0012, 0x00); // Deselect Master page
    writeAdcReg(0x0011, 0xFF); // Select ADC page
    writeAdcReg(0x0083, 0x07); // Additional analog trims
    writeAdcReg(0x005C, 0x00);
    writeAdcReg(0x005C, 0x01);
    writeAdcReg(0x0011, 0x00); // Deselect ADC page
    writeAdcReg(0x4001, 0x00); // Select ??
    
    writeAdcReg(0x0012, 0x04); // Select Master page
    writeAdcReg(0x0058, 0x20); // SyncB Polarity is inverted
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x01);
    writeAdcReg(0x4004, 0x68); // Select main digital page for Ch B
    writeAdcReg(0x60A2, 0x08); // Nyquist zone specification enabled
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x68); // Select main digital page for Ch A
    writeAdcReg(0x60A2, 0x08); // Nyquist zone specification enabled
    
    writeAdcReg(0x4001, 0x00);
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x01);
    writeAdcReg(0x4004, 0x68); // Select main digital page for Ch B
    writeAdcReg(0x6049, 0x80); // Special settings for Ch B
    writeAdcReg(0x6042, 0x20);
    writeAdcReg(0x4003, 0x00); // Select main digital page for Ch A ?
    writeAdcReg(0x6044, 0x01);
    writeAdcReg(0x6068, 0x04);
    writeAdcReg(0x60FF, 0xC0);
    writeAdcReg(0x60A9, 0x03);
    writeAdcReg(0x60AB, 0x77);
    writeAdcReg(0x60AC, 0x01);
    writeAdcReg(0x60AD, 0x77);
    writeAdcReg(0x60AE, 0x01);
    writeAdcReg(0x6096, 0x0F);
    writeAdcReg(0x6097, 0x26);
    writeAdcReg(0x608F, 0x0C);
    writeAdcReg(0x608C, 0x08);
    writeAdcReg(0x6080, 0x0F);
    writeAdcReg(0x6081, 0xCB);
    writeAdcReg(0x607D, 0x03);
    writeAdcReg(0x6056, 0x75);
    writeAdcReg(0x6057, 0x75);
    writeAdcReg(0x6053, 0x00);
    writeAdcReg(0x604B, 0x03);
    writeAdcReg(0x6049, 0x80);
    writeAdcReg(0x6043, 0x26);
    writeAdcReg(0x605E, 0x01);
    writeAdcReg(0x6042, 0x38);
    writeAdcReg(0x605A, 0x04);
    writeAdcReg(0x6071, 0x20);
    writeAdcReg(0x6062, 0x00);
    writeAdcReg(0x6098, 0x00);
    writeAdcReg(0x6099, 0x08);
    writeAdcReg(0x609C, 0x08);
    writeAdcReg(0x609D, 0x20);
    writeAdcReg(0x60BE, 0x03);
    writeAdcReg(0x6069, 0x00);
    writeAdcReg(0x6045, 0x10);
    writeAdcReg(0x608D, 0x64);
    writeAdcReg(0x608B, 0x20);
    writeAdcReg(0x6000, 0x00);
    writeAdcReg(0x6000, 0x01);
    writeAdcReg(0x6000, 0x00);
    writeAdcReg(0x4002, 0x00);
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch B
    writeAdcReg(0x6002, 0x0F); // 12-bit mode, JESD MODE0 = 3
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch A
    writeAdcReg(0x7002, 0x0F); // 12-bit mode, JESD MODE0 = 3
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch B
    writeAdcReg(0x6037, 0x01); // PLL mode = 16X
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch A
    writeAdcReg(0x7037, 0x01); // PLL mode = 16X
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch B
    writeAdcReg(0x6032, 0x00); // 3C Lane 0 de-emphasis = -6.2 dB
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch A
    writeAdcReg(0x7032, 0x00); // Lane 0 de-emphasis = -6.2 dB
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch B
    writeAdcReg(0x6033, 0x00); // Lane 1 de-emphasis = -6.2 dB
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch A
    writeAdcReg(0x7033, 0x00); // Lane 1 de-emphasis = -6.2 dB
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch B
    writeAdcReg(0x6034, 0x00); // Lane 2 de-emphasis = -6.2 dB
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch A
    writeAdcReg(0x7034, 0x00); // Lane 2 de-emphasis = -6.2 dB
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch B
    writeAdcReg(0x6035, 0x00); // Lane 3 de-emphasis = -6.2 dB
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch A
    writeAdcReg(0x7035, 0x00); // Lane 3 de-emphasis = -6.2 dB
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch B
    writeAdcReg(0x6001, 0x80); // Enables number of frames per multiframe
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch A
    writeAdcReg(0x7001, 0x80); // Enables number of frames per multiframe
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch B
    writeAdcReg(0x6007, 0x0F); // Frames per multiframe (K) = 16
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch A
    writeAdcReg(0x7007, 0x0F); // Frames per multiframe (K) = 16
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x69); // Select JESD digital page for Ch A
    writeAdcReg(0x7036, 0x40); // Use GPIO4 for Sync
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x01);
    writeAdcReg(0x4004, 0x68); // Select main digital page for Ch B
    writeAdcReg(0x60A2, 0x09); // 2nd Nyquist zone
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x68); // Select main digital page for Ch A
    writeAdcReg(0x60A2, 0x09); // 2nd Nyquist zone
    
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x20);
    writeAdcReg(0x4002, 0xF8); // Nonlinearity Optimization for Ch A
    writeAdcReg(0x603C, 0x00);
    writeAdcReg(0x603D, 0xFF);
    writeAdcReg(0x603E, 0xEA);
    writeAdcReg(0x603F, 0x00);
    writeAdcReg(0x6040, 0xFA);
    writeAdcReg(0x6041, 0xFD);
    writeAdcReg(0x6042, 0x02);
    writeAdcReg(0x6043, 0xFD);
    writeAdcReg(0x6044, 0x06);
    writeAdcReg(0x6045, 0x02);
    writeAdcReg(0x6053, 0x00);
    writeAdcReg(0x6054, 0xFF);
    writeAdcReg(0x6055, 0xEB);
    writeAdcReg(0x6056, 0x00);
    writeAdcReg(0x6057, 0xF9);
    writeAdcReg(0x6058, 0xFD);
    writeAdcReg(0x6059, 0x03);
    writeAdcReg(0x605A, 0xFE);
    writeAdcReg(0x605B, 0x04);
    writeAdcReg(0x605C, 0x00);
    writeAdcReg(0x606A, 0x00);
    writeAdcReg(0x606B, 0xFF);
    writeAdcReg(0x606C, 0xEA);
    writeAdcReg(0x606D, 0x00);
    writeAdcReg(0x606E, 0xF9);
    writeAdcReg(0x606F, 0xFD);
    writeAdcReg(0x6070, 0x02);
    writeAdcReg(0x6071, 0xFD);
    writeAdcReg(0x6072, 0x04);
    writeAdcReg(0x6073, 0x00);
    writeAdcReg(0x6081, 0x00);
    writeAdcReg(0x6082, 0x00);
    writeAdcReg(0x6083, 0xEC);
    writeAdcReg(0x6084, 0xFF);
    writeAdcReg(0x6085, 0xF8);
    writeAdcReg(0x6086, 0xFE);
    writeAdcReg(0x6087, 0x02);
    writeAdcReg(0x6088, 0xFD);
    writeAdcReg(0x6089, 0x04);
    writeAdcReg(0x608A, 0x00);
    writeAdcReg(0x6098, 0x02);
    writeAdcReg(0x6099, 0xFF);
    writeAdcReg(0x609A, 0x02);
    writeAdcReg(0x609B, 0x01);
    writeAdcReg(0x609C, 0x02);
    writeAdcReg(0x609D, 0x05);
    writeAdcReg(0x609E, 0x01);
    writeAdcReg(0x609F, 0x03);
    writeAdcReg(0x60A0, 0x02);
    writeAdcReg(0x60A1, 0x00);
    writeAdcReg(0x60AF, 0x03);
    writeAdcReg(0x60B0, 0xFF);
    writeAdcReg(0x60B1, 0x01);
    writeAdcReg(0x60B2, 0x01);
    writeAdcReg(0x60B3, 0x03);
    writeAdcReg(0x60B4, 0x04);
    writeAdcReg(0x60B5, 0x02);
    writeAdcReg(0x60B6, 0x04);
    writeAdcReg(0x60B7, 0xFE);
    writeAdcReg(0x60B8, 0x00);
    writeAdcReg(0x60C6, 0x03);
    writeAdcReg(0x60C7, 0xFF);
    writeAdcReg(0x60C8, 0x01);
    writeAdcReg(0x60C9, 0x01);
    writeAdcReg(0x60CA, 0x02);
    writeAdcReg(0x60CB, 0x05);
    writeAdcReg(0x60CC, 0x01);
    writeAdcReg(0x60CD, 0x04);
    writeAdcReg(0x60CE, 0xFE);
    writeAdcReg(0x60CF, 0x00);
    writeAdcReg(0x60DD, 0x02);
    writeAdcReg(0x60DE, 0x00);
    writeAdcReg(0x60DF, 0x01);
    writeAdcReg(0x60E0, 0x01);
    writeAdcReg(0x60E1, 0x02);
    writeAdcReg(0x60E2, 0x05);
    writeAdcReg(0x60E3, 0x01);
    writeAdcReg(0x60E4, 0x04);
    writeAdcReg(0x60E5, 0xFE);
    writeAdcReg(0x60E6, 0x00);
    writeAdcReg(0x60F4, 0xFE);
    writeAdcReg(0x60F5, 0xFF);
    writeAdcReg(0x60FB, 0x01);
    writeAdcReg(0x60FC, 0x01);
    
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x20);
    writeAdcReg(0x4002, 0xF9);
    writeAdcReg(0x6074, 0x00);
    writeAdcReg(0x6075, 0xFF);
    writeAdcReg(0x6076, 0xEB);
    writeAdcReg(0x6077, 0x00);
    writeAdcReg(0x6078, 0xFA);
    writeAdcReg(0x6079, 0xFC);
    writeAdcReg(0x607A, 0x03);
    writeAdcReg(0x607B, 0xFD);
    writeAdcReg(0x607C, 0x04);
    writeAdcReg(0x607D, 0x02);
    writeAdcReg(0x608B, 0xFF);
    writeAdcReg(0x608C, 0xFF);
    writeAdcReg(0x608D, 0xEA);
    writeAdcReg(0x608E, 0x00);
    writeAdcReg(0x608F, 0xF9);
    writeAdcReg(0x6090, 0xFE);
    writeAdcReg(0x6091, 0x02);
    writeAdcReg(0x6092, 0xFD);
    writeAdcReg(0x6093, 0x04);
    writeAdcReg(0x6094, 0x00);
    writeAdcReg(0x60A2, 0x00);
    writeAdcReg(0x60A3, 0xFF);
    writeAdcReg(0x60A4, 0xEA);
    writeAdcReg(0x60A5, 0x00);
    writeAdcReg(0x60A6, 0xF9);
    writeAdcReg(0x60A7, 0xFD);
    writeAdcReg(0x60A8, 0x02);
    writeAdcReg(0x60A9, 0xFD);
    writeAdcReg(0x60AA, 0x02);
    writeAdcReg(0x60AB, 0x02);
    writeAdcReg(0x60B9, 0x00);
    writeAdcReg(0x60BA, 0x00);
    writeAdcReg(0x60BB, 0xEB);
    writeAdcReg(0x60BC, 0x00);
    writeAdcReg(0x60BD, 0xF8);
    writeAdcReg(0x60BE, 0xFE);
    writeAdcReg(0x60BF, 0x02);
    writeAdcReg(0x60C0, 0xFD);
    writeAdcReg(0x60C1, 0x02);
    writeAdcReg(0x60C2, 0x02);
    writeAdcReg(0x60D0, 0x02);
    writeAdcReg(0x60D1, 0x00);
    writeAdcReg(0x60D2, 0x02);
    writeAdcReg(0x60D3, 0x01);
    writeAdcReg(0x60D4, 0x02);
    writeAdcReg(0x60D5, 0x05);
    writeAdcReg(0x60D6, 0x01);
    writeAdcReg(0x60D7, 0x03);
    writeAdcReg(0x60D8, 0x02);
    writeAdcReg(0x60D9, 0x02);
    writeAdcReg(0x60E7, 0x02);
    writeAdcReg(0x60E8, 0xFF);
    writeAdcReg(0x60E9, 0x01);
    writeAdcReg(0x60EA, 0x01);
    writeAdcReg(0x60EB, 0x03);
    writeAdcReg(0x60EC, 0x04);
    writeAdcReg(0x60ED, 0x02);
    writeAdcReg(0x60EE, 0x04);
    writeAdcReg(0x60EF, 0x00);
    writeAdcReg(0x60F0, 0x00);
    writeAdcReg(0x60FE, 0x02);
    writeAdcReg(0x60FF, 0xFF);
    
    writeAdcReg(0x4002, 0xFA);
    writeAdcReg(0x6000, 0x01);
    writeAdcReg(0x6001, 0x01);
    writeAdcReg(0x6002, 0x02);
    writeAdcReg(0x6003, 0x04);
    writeAdcReg(0x6004, 0x02);
    writeAdcReg(0x6005, 0x04);
    writeAdcReg(0x6006, 0x00);
    writeAdcReg(0x6007, 0x00);
    writeAdcReg(0x6015, 0x02);
    writeAdcReg(0x6016, 0x00);
    writeAdcReg(0x6017, 0x01);
    writeAdcReg(0x6018, 0x01);
    writeAdcReg(0x6019, 0x02);
    writeAdcReg(0x601A, 0x04);
    writeAdcReg(0x601B, 0x02);
    writeAdcReg(0x601C, 0x03);
    writeAdcReg(0x601D, 0x00);
    writeAdcReg(0x601E, 0x00);
    writeAdcReg(0x602C, 0xFE);
    writeAdcReg(0x602D, 0xFF);
    writeAdcReg(0x6033, 0x01);
    writeAdcReg(0x6034, 0x01);
    
    writeAdcReg(0x4002, 0x00);
    writeAdcReg(0x4003, 0x00);
    writeAdcReg(0x4004, 0x68);
    writeAdcReg(0x6068, 0x00);
    writeAdcReg(0x0011, 0x00);
    writeAdcReg(0x0012, 0x04);
    writeAdcReg(0x005C, 0x87);
    writeAdcReg(0x0012, 0x00);

    Thank you,

    DT

  • Hi DT, I’ll verify this config on an ADC32RF45EVM at 1500 MSPS with your mode on Tuesday. If it works as expected on the EVM, we can look into FPGA configuration. What is the SYSREF frequency you are using? Regards, Vijay
  • Hi Vijay,

    We are using a sysref freq of 2.34375 MHz.

    Thank you,

    DT

  • Hi DT,

    JESD SYNCB polarity is inverted in this config. Is this taken into consideration?

    You can try without SYNCB polarity inversion by changing line 54 in the config file as below:

    "writeAdcReg(0x0058, 0x00); // SyncB Polarity is inverted"

    Regards,

    Vijay