Hi,
We're currently having a problem where we lose SYNC between the ADC32RF45 and the JESD204 core in our Xilinx FPGA.
After initialization of the ADC the following is received on the output of the Xilinx JESD core. We appear to lose sync multiple times until all we receive is "BCBC" on the JESD lanes.
Upon resetting the JESD cores we get the following:
Note that the duration of rx_tvalid is not always the same.
When we review the Xilinx JESD204 cores registers, the Link Error Status register indicates that every lane received unexpected K-character(s).
Does anyone have any insight as to why this would be happening?
Thank you,
DT