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DAC7760: Use on SPI bus w/ADC?

Matt Conway
Prodigy 50 points
Part Number: DAC7760
Other Parts Discussed in Thread: ADS8681, , DAC8760

Hello,

I took over a design, which was started by another engineer. Currently, the DAC7760 and ADS8681 are on the same SPI bus. However, as I am reading the DAC7760 datasheet, what is being used as a chip select in our schematic does not appear to be a chip select at all; it is essentially a shift register output latch (it is even labelled LATCH). That being said, it appears that you can't really bus the DAC7760 with another device without an additional chip (like a buffer with an enable to turn the MOSI line off). This appears to be confirmed by the notes in the datasheet that mention non-24bit frames will affect the DAC7760 output. Meaning, if I send a 32 bit frame to the ADC, the DAC will not ignore it (there is no CS), so when I send the 24bit frame to the DAC, the DAC has actually received 56 bits and could mis-behave.

Am I interpreting the datasheet correctly? Do I really need to implement a secondary chip to have a SPI bus? Has anyone successfully implemented a SPI bus for the DAC7760?

  • 0
    Prodigy 50 points

    Upon re-reading the SPI portion of the datasheet, I may have ping'ed this question early. The device does not appear to be designed for buss-ing without some level of external components (I do not see anything about tri-stating the MISO line). It appears that this isn't necessarily uncommon.

    However, it does appear that the context of the datasheet statement:          "Providing more or less than 24 SCLK cycles before the rising edge of LATCH results in results in incorrect data..."          is most likely only referring to non-integer multiple of 24bits ( a few extra or too few, which would offset the shift register), not receiving any number of bits and concluding with a correct 24bit frame.

    That being said, I think I can bus the DAC7760 with a tri-state buffer on the MISO line only. This would allow other slaves to communicate without contention. The LATCH signal is not a CS, but can function the same way, just different timing. Instead of asserting the signal for an entire message (CS), only assert the LATCH at the end of a correct 24bit message. I may add an AND gate on SCLK as well, just for cleanliness.

    I think this is the solution to bus the DAC7760, but comments are still appreciated. 

  • 0 in reply to Matt Conway
    TI__Guru 53333 points

    Hi Matt,

    I will take a look at this over the weekend and get back to you on monday.

    Thanks,

    Paul

  • 0 in reply to Paul_Frost
    TI__Guru 53333 points

    Hi Matt,

    Are you daisy-chaining the DAC with the ADC? and by that I mean you would be connecting the MOSI line from the MCU to the SDI pin of the DAC8760, then connecting the SDO pin of the DAC8760 to the SDI pin of the ADC?  Or are you shorting the MOSI line to the SDI pins of both devices?

    The DAC8760 can support the daisy-chain mode, but the parallel mode will be difficult without a separate chip select.

    See section "8.3.11.1 The DACx760 Shares the SPI Bus With Other Devices (Non-DACx760)" of the PDS.

    Thanks,

    Paul

  • 0 in reply to Paul_Frost
    Prodigy 50 points

    Paul,

    No, I was intending on parallel-ing the two units, which would mean the MOSI lines would be shorted, as well as the MISO lines. I would like to be able to read from the DAC, but I don't see the daisy-chain pass-through mode in the ADC, so I think it would need to be bussed to get full read and write capabilities to both ICs.

    I read through that section and section 8.5, butI think you have answered my question, I need to use external components to give the SDO line a tri-state/high impedance state and although it would not be necessary because of the LATCH operation, I could add a high-speed AND gate to the MOSI line for cleanliness.

    Thank You,

    Matt

  • 0 in reply to Matt Conway
    TI__Guru 53333 points

    Hi Matt,

    I think your understanding is correct.  Maybe you could utilize two GPIO pins from the MCU as different chip selects?

    Thanks,
    Paul

  • 0 in reply to Paul_Frost
    Prodigy 50 points

    Paul,

    I think that is what I will do. I am looking at putting a tri-state buffer on the MISO and utilizing two GPIO lines for the DAC (one for the tri-state buffer/AND gate and one for the latch). Then I will have a third for the ADC CS. I think this will work out well, thank you for the assistance and clarifications.

    -Matt