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ADC12J4000: Calibration Requirements

Part Number: ADC12J4000

We are using the ADC12J4000 is our application and are seeing a Fs/4 -Fin image that appears larger than quoted in the datasheet. Specifically, a strong narrow band noise input at one frequency - but not saturating the ADC - produces also a low level Fs/4 -Fin image in the digital spectrum. We are using FG calibration including timing optimisation after the system has stabilised and the ADC cards are housed in a temperature controlled air conditioned environment so the operating temperature does not vary significantly.

Are there any special requirements for the calibration to be optimal and achieve the numbers in the datasheet? Specifically, is it necessary to mute the RF input to the device while the FG calibration is running? In our system the RF is input is fed with an active signal during the calibration, but this does not exceed any of the max ratings or even clip the ADC input range.

Regards,

Paul Roberts

  • Hi Paul,

    I can look more into the calibration questions this week. Are you calibrating once the ADC is thermally soaking and equalized? Not just on initial power up?

    Also, if you can share a bit more on how you are test the ADC that could help as well. Is this your application board? or our EVM for your analysis? In either case, what are you using for the analog input source an sampling clock? Details on the setup will help.

    Thank you,

    Rob

  • Hi Rob,

    Yes. We are calibrating after the devices have well stabilized, sometimes after running continuously for months in the temperature stabilised environment.

    This is a custom board we are using. The signal source is real world radio-background. We are running a sampling clock in this particular case at 2560 MHz. This is produced using an associated PLL based on an LT6946 Synthesiser. The band between 1280 and 2560 MHz is sampled (somewhat less due to anti-alias filter) so is using direct sampling of the second Nyquist zone. We are finding that the strong cellullar signal around 1800 MHz is also producing a low level image around 1320 MHz exactly as predicted  for the 4 way time interleaving Fs/4 -Fin that is much stronger than expected so wondering if we are doing something wrong with the calibration. By using a step attenuator we can step the RF power at the input to the ADC and see the image step in exact proportion showing it is related to the strong signal at 1800, which is the dominant signal in the spectrum. Likewise as the 1800 MHz signal pulses in power the image pulses with 100% correlation.

    We have several ADC boards in operation and they each show this effect to varying levels, some much more than others. We have swapped the RF inputs over and the signal processing backend and the effect stays with the particular ADC. The RF front end is extremely stable comprised of a cryogenically cooled LNA and temperature controlled post amplification.

    The ADC data is transferred to an FPGA were a digital filter bank is used to produce many frequency sub-channels and these can then be integrated for some ms to seconds, which is how we analyse the full spectrum and test this effect.

    As I mentioned the signal source is present during the foreground cal so i want to check that it is not a requirement to mute this during the foreground CAL?

    Any help is appreciated.

    Regards,

    Paul Roberts

  • Hi Paul,

    Sorry for the delay, I am checking with design. I hope to have an answer back soon for you.

    Regards,

    Rob

  • Hi Paul,

    I have some feedback from the designers....

    It is highly unlikely that having the source signal on could affect the foreground calibration to create Fs/4-Fin spurs. The input would have to be a large single tone very close to Fclk/4. 

    We need to understand if it is the result of gain mismatch or timing mismatch. This can be extracted from a complex FFT, if your system is flexible and allows for this level of diagnosis. 

    Otherwise, a simpler approach is to look at this spur magnitude versus Fin.  If the Fs/4-Fin spur is flat across frequency, then it is probably a gain spur which could be related to foreground calibration.  If spur magnitude increases with signal input frequency, then it will result from either timing or BW mismatch. Timing mismatch could be due to the part, or if a Fclk/4 signal coupled into the ADC’s clock at the board level.

    Is either approach something you can try out in your system and let me know your results to help further troubleshoot?

    Regards,

    Rob

  • Thanks Rob,

    The complex FFT approach is possible. I have the ability to collect 64k raw samples at a time so I can perform the signal processing on buffers of this size. I can capture any number of buffers and accumulate the results of individual complex FFTs on 64k samples at a time. Will this be sufficient to perform the diagnosis? Could you please explain the signal processing steps I need to do via the complex FFT to separate the gain from timing error effects?

    I will also setup a test system to check how the effect varies with frequency.

    I'd like to check that how we setup and calibrate the ADC is correct also, could you please check if the code fragment below that shows the register writes to setup the ADC is doing anything wrong that could contribute to a calibration error.

    Thanks,

    paul

    -- Setup ADC

    WRITE 0x0002 <= 0x00 // Bring the ADC out of low-power mode if necessary
    WRITE 0x0021 <= 0x00 // Reset all registers
    WRITE 0x0021 <= 0x01 // Deassert reset
    WRITE 0x0030 <= 0x00 // SYSREF receiver and processor off
    WRITE 0x0040 <= 0x04 // Set serialiser pre-emph for high speed PCB
    WRITE 0x0066 <= 0x03 // Foreground cal with timing optim enabled
    WRITE 0x002B <= 0x13 // Change reserved register to proper setting
    WRITE 0x0208 <= 0x07 // Change ovr range processing to longest interval
    WRITE 0x0051 <= 0x84 // Calibration optimised for large signals
    WRITE 0x0201 <= 0x0E // Scrambler off, KM1=3, DDR, JESD disabled
    WRITE 0x0200 <= 0x30 // Select BYPASS mode , 2's Complement Data format
    WRITE 0x0202 <= 0x00 // P54 PLL off, SE SYNC, Normal data mode
    WRITE 0x0201 <= 0x0E // Scrambler off, KM1=3, DDR
    WRITE 0x0050 <= 0x0E // Initiate a foreground calibration
    WAIT <100ms // Poll every ms for up to 100ms until calibration completes
    CHECK 0x005B & 0x3 == 3 // Calibration complete (polled until true in loop)
    WRITE 0x0205 <= 0x18 // Clear JESD alignment status
    WRITE 0x0201 <= 0x0F // JESD Enable (and Scrambler off, KM1=3, DDR)
    WRITE 0x0032 <= 0x80 // set SYSREF delay to emp value determined from lab test with default cable lengths (0x8C)
    WRITE 0x0030 <= 0x80 // enable SYSREF receiver and SYSREF processor off
    WRITE 0x0030 <= 0xF0 // enable SYSREF receiver and enable SYSREF processor and clear status bits
    WRITE 0x0030 <= 0xC0 // enable SYSREF receiver and enable SYSREF processor and release status bit reset
    WAIT 1ms
    CHECK 0x0031 & 0xC0 == 0x80 // SYSREF Captured & clean

  • Hi Paul,

    Basically setup the system as you normally do, then to perform this test is sweep Fin from the lower frequency band to the highest frequency band used in your application.

    Collect the FFT and all the associated spur magnitude, Fs/4, Fs/2, SFDR, HD2/3 at each frequency, collect both the real and imaginary part.

    I will review the spi writes tomorrow to see if anything is off. At first glance though, everything appears to be okay.

    Regards,

    Rob

  • Paul,

    This setup you shows appear correct. My next thoughts would be noise coupling at Fs/4 into the input clock or signal. Can you provide more info about the clock source? Can you send your schematic?

    Regards,

    Jim