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ADC32RF45EVM: Not getting Reference frequency from LMK04828

Part Number: ADC32RF45EVM
Other Parts Discussed in Thread: ADC32RF45, LMX2582, LMK04828,

Hello sir

We are using custom board of ADC32RF45, schematic of the board is same as Ti 

we are giving RF input is 150 MHZ.

we are using on board oscillator clock i.e. 122.88 MHZ

LMX2582 is giving clocks to ADC.

we are using ADC32RFXX EVM GUI .

Internal clock frequency is 1536 Msps

we are using DDC single band with complex ouput

decimation is x4

PLL mode is 40x

LMFS is 4 4 2 1

after programming EVM

DDC configurations are :   sampling clock is 3000 MHZ 

JESD204b configurations are 

k = 8

sync is requested

k28.5 ADC mixed data

LMK04828 output clock

clk0&clk1 => divided by 8

These are the configurations we have set in GUI, we are not getting reference clk which is going to FPGA. Please suggest us to get reference clock. 


Roja Veereddy

  • Hi Roja Veereddy,

    Have you programmed the USB product description of your custom board to "ADC32RFxx EVM" using a program like FTDI's FT_Prog? If not GUI will not detect the board. If board is detected by GUI,you should get green light on the top right corner beside USB status.

    As mentioned in the orignal post () , I verified that 192 MHz FPGA clock output from LMK04828 is configured as expected on  ADC32RF45EVM FMC pins. If you are using the same schematic as EVM on your custom board and USB is connected to GUI, it is supposed to function the way as TI EVM. 



  • Hai sir

    Thank you for suggesting, now we are getting FPGA reference clock frequency is around 192 MHZ.

    But Tranceiver output is not coming including lane clock .

    In tranceiver rx data rate is 5000Mbps

    CDR reference clock frequency is 125 MHZ.

    still we didn't get Lane clock from the tranceiver.

    Please, could you suggest me what parameters we need to add to get tranceiver output and jesd204b output.


    Roja Veereddy

  • Hi Roja Veereddy,

    With sampling rate 1536 MSPS, decimation /4 complex and LMFS 4421,  Each ADC channel's I or Q channel output data rate is 1536/4 = 384 MSPS (16-bit samples) and JESD lane rate is 7.68 Gbps. Please make sure the FPGA is appropriately configured for this.



  • Hello sir,

    Thank you for suggesting to resolve the issue.

    JESD lane rate is 7.68 Gbps.

    Please could you tell me the calculation for this

    because we are using 12.5 Gbps rate


    Roja Veereddy

  • Hi Roja Veereddy,

    Below are your mode parameters:

    Sampling rate = 1536 MSPS

    decimation: /4

    JESD LMFS: 4421 (L is number of lanes =4)

    From the above, we can calculate output data rate of each channel is 1536/4 = 384 MSPS

    JESD output has four channels, AI, AQ, BI and BQ each at a data rate of 384 MSPS

    Total data rate = 4 * 384 = 1536 MSPS

    Each sample has 16 bits. So total bit rate = 1536 * 16 = 24576 Mbps

    After 8b/10b encoding, total bit rate = 24576 * (10/8) = 30720 Mbps

    There are 4 active JESD lanes. So lane rate = 30720 / 4 = 7680 Mbps = 7.68 Gbps