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ADS4142: ADS4142 Clock source from the FPGA

Kwok Luo
Prodigy 130 points
Part Number: ADS4142
Other Parts Discussed in Thread: CDCE72010, LMK04228, CDCLVP1102

Hello,

I am planning to use the ADS4142 to read in my analog signal. For this ADC, a clock driver is required in order to get the low jitter + low noise for high sampling rate. I have also seen that the LVPECL clock driver is required.

My question is which LVPECL clock driver should I use. The idea is that the clock signal(single-ended clock signal ,which comes from the FPGA, should be institute to the clock driver. Afterwards, the clock driver  drives the differential CLKP and CLKM of the ADS4142.

Best regards,

Kwok

  • 0
    TI__Mastermind 18095 points

    Typically the clock from the FPGA is not low jitter.  The approach is to use a clock generator that can supply the ADC clock and the synchronized clock to the FPGA.  The ADS4142 EVM uses the CDCE72010 clock generator device.  You can also check out a device like the LMK04228.

    --RJH

  • 0 in reply to RJ Hopper
    Prodigy 130 points

    Is it also possible to use a clock buffer (FPGA clock signal to the clock buffer. From the clock buffer to the CLKP and CLKM of the ADS4142)?

  • 0 in reply to Kwok Luo
    TI__Mastermind 18095 points

    If you mean to use the FPGA clock as a reference signal to the clock chip that then synchronizes its own internal (clean) VCO to and then outputs that clock (or a divided down output) to the ADC...then yes...this is acceptable.

    I do not think a simple buffer will improve the FPGA clock phase noise significantly and will be a poor quality clock to the ADC.  It all depends on the quality of the FPGA clock and the amount of SNR degradation from a poor phase noise clock that can be accepted.

    --RJH

  • 0 in reply to RJ Hopper
    Prodigy 130 points

    Thank you for your response. I have also seen in the datasheet of ADS4142 under section 'typical application' or page 72, that they use LVPECL clock driver. Which Output format Do I need in fact need (The clock driver is terminated with a LVDS termination)?

    To sum up, it's recommended to use a clock generator ic  instead of a clockdriver/clock buffer (CDCLVP1102) with an appropiate termination depending on the output format of the IC-chip. Am I right?

  • 0 in reply to Kwok Luo
    TI__Guru* 91947 points

    Kwok,

    You are correct. You should use a clock generator that has low phase noise. You can use either LVDS or LVPECL mode.

    Regards,

    Jim