Other Parts Discussed in Thread: DAC3174
I am struggling to get any passing results from the built-in iotest feature of the DAC3171. Additionally, there is some odd behavior in config5 register (addr 0x05) that I cannot reconcile.
I am using an FPGA to drive the full-word interface (14b) in SYNC_ONLY mode. Both DATACLK and DACCLK are at 122.88MHz. Initialization sequence is as follows:
1) Keep RESET_N and TXENABLE at '0'
2) Apply power supplies to the DAC
3) Wait a long time (>2sec) for power supplies to settle
4) Turn on DACCLK and DATACLK
5) Issue reset pulse (100us active)
6) Write config0 register with value 0x068D to enable 4-wire interface mode
7) Write config10 register with value 0xF1A0 to disable the temp sensor and DACB
8) Write config21 register with value 0x517F to disable SLEEP to various parts of the IC
9) Write config12-config19 registers with the following iotest values:
0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
10) Write config1 register with value 0xF00E to enable iotest_ena, 64cnt_ena, and the FIFO alarms
11) Set TXENABLE to '1'
12) Start FPGA data interface, which sends the above data pattern and issues SYNC along with the 0x1 word every time the pattern repeats
When performing several read-write-read sequences to config4 and config5 registers (writing 0 to clear them) produces the following values:
config4 = 0x0001
config5 = 0x0008
My first issue is that I have tried everything I can think of to get the DAC to recognize the iotest pattern, but it never yields a "passing" result unless I send the same data word endlessly (no bits on the data interface changing). I haven't been able to get an oscilloscope to measure/validate the outputs, but I have simulated the HDL and have confidence that it is operating and constrained correctly.
My second issue is the value of config5 register... bit3 is "reserved" according to the datasheet, but it seems to indicate an iotest error on the lower 7 bits of the interface. If I change the first word of the above test pattern from 0x0001 to 0x0080 and adjust config12 register value to the same, I see config5 register value goes to 0x0010, which is documented as the iotesta error alarm. Config4 register value shows a reasonable value of 0x0080 indicating that b7 has failed to match during the iotest.
I need to understand whether the iotest is functioning as expected when operating in my configuration. I would also like to understand why config5's behavior does not match the datasheet's description. According to the DAC3174 datasheet, bit 3 indicates an iotestb error... which makes me wonder if the DAC is not configured correctly, but I cannot find a reason why this would be the case.
Please advise.
