ADS6125: External clock rising edge

Mark Philip Felipe

Part Number: ADS6125

Hi Team, we would like to confirm when is an acceptable range of time from our external clock rising edge (54Mhz clock) to when the input data can be sampled in the FPGA?

Thank you for your inputs.

Regards,

Mark

over 5 years ago

0 jim s over 5 years ago

TI__Guru* 91947 points

Mark,

We will need more info. Is this external clock used to clock the ADC and the FPGA? If so, is there a delay between these clocks? Is this CMOS or LVDS mode?

Regards,

Jim

0 Mark Philip Felipe over 5 years ago in reply to jim s

TI__Genius 10870 points

Hi Jim,

Yes, the clock is used for both the ADC and the FPGA. We don't expect a delay between the clock given to the ADC and the same clock used by the FPGA and it is on LVDS mode.

Regards,

Mark

0 jim s over 5 years ago in reply to Mark Philip Felipe

TI__Guru* 91947 points

Mark,

I would estimate you would have 5ns of setup and 2ns of hold time if using the rising edge. This will be data that is clocked out of the ADC on the falling edge of CLKOUT. There are a couple of register settings that will allow you to adjust this timing if needed.

Regards,

Jim

Data converters

Data converters forum

ADS6125: External clock rising edge