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DAC39J82: Can the SYSREF pins interface with a LVDS fanout chip?

Part Number: DAC39J82

Hello

We want to use a LVDS chip (IDT 8P34S1102NLGI) to connect to the SYSREF pins of the DAC39J82.  According to the IDT datasheet, it lists its DIFFERENTIAL OUTPUT VOLTAGE as 247mV - 454mV.

Can the DAC see this differential voltage?  Its weird that the SYSREF LVPECL inputs have Vcm = 0.5V yet most LVPECL VCM are much larger.  Thats why I am hoping that the IDT LVDS fanout buffer will still work.

Please assist.  

The IDT datasheet is here:

Thanks,

Layne

 

  • Layne,

    The DAC requires a minimum of 400mV diff input and the IDT part has a minimum of 247mV. I would not recommend using this part.

    Regards,

    Jim

  • Hi jim


    Thanks for your quick response.

    Do you have any recommended DC-coupled fanout drivers that will sit between a LMK04828B and DAC39J82 SYSREF inputs?  Something with LOW noise?

    thanks

  • by the way, the IDT part was chosen for its "low additive phase-noise".  Does TI make such a part that will work for my applicaiton?

    thanks

  • Layne,

    I suggest you post this to the high speed clocking forum and send them a block diagram of your system clocking. They should be able to provide you with the best solution.

    Regards,

    Jim

  • hi Jim

    actually I got a more specific question.  What is the range for the common mode voltage for the SYSREF pins?  The datasheet only specs 0.5V as typical.  

    I found a lvpecl driver that has VOH = 1.6V (TYP), VOL = 0.85V (TYP).  This implies that the SWING is 750mV and a VOCM of 1.2V.  

    Will this work for the SYSREF pins?

    thanks

  • Layne,

    The CM range is 0.25V to 0.75V. The inputs are self biased so you could also AC couple these as another option.

    Another option is to find a LCPECL driver. This is the output mode used by the LMK device on the customer EVM with a voltage divider used to bring down the swing and CM.

    Why are you not using the LMK to drive the SYSREF? This part was designed for this function and has 7 pairs of device clock/SYSREF clocks available.

    Since you are looking into using a separate device to drive SYSREF, you must be careful to meet setup and hold times for SYSREF with respect to the DACCLK. The LMK has many features to make this timing meet these requirements.

    Regards,

    Jim 

  • HI jim

    we are using the lmk to feed a clock to 4dacs and 4adc and a xilinx.  the lmk doesnt have enough i/o for our needs.  furthermore we need a dc-coupled connection because we generate a pulse on the SYSREF that is more OFF than ON.  Sort of like the GPS 1PPS signal.  if we use any ac-coupling that pulse will never be seen by any receiver.

    wow...i didnt realize that the CM range is so low. this info would be great to add to the datasheet.  only the typical values are listed.

    is the spec for the DACCLKP/N the same as the SYSREF, where the VICM is 0.25 to 0.75V?

    thanks for all your help in this matter

  • Layne,

    There is no min/max. The common mode is established by the bias network internally. As long as the clock driver present a higher impedance than the clock internal bias network, there shouldn’t be a min/max requirement. Since the clock is continuously running, you should AC couple this input and not have to worry about the CM.

     

    Regards,

     

    Jim