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ADS1216: Whether ADC front end needs op amp

Part Number: ADS1216

4 ~ 20mA signal acquisition, sinc3 mode.

1. Whether ADC front end needs op amp.

2. What is the ADC acquisition speed in  Fast Settling  mode? Using 4.9152MHz frequency, PGA is 1, speed bit is 1, ADC output code speed is 4.915/256 = 19.2Hz, is the calculation correct?

  • Hello,

    1.)  The ADS1216 features an integrated buffer and PGA, therefore unless additional signal conditioning such as gain/level/filtering options are desired before the PGA, an external buffer is not required. 

    2.)  I believe you're referring to the data rate "f_DATA" which is calculated by "f_MOD/Decimation Ratio.   The f_MOD frequency will be:  4.915MHz/256= 19.199kHz which matches your calculation.  The final output data will be this value divided by the decimation ratio that's configured in the 

    DEC0 (Address 08h) Decimation Register (least significant 8 bits) Reset value = 80h.
    M/DEC1 (Address 09h) Mode and Decimation Register

    The decimation value is defined with 11 bits for a range of 20 to 2047. This register is the least significant eight bits. The three most significant bits are contained in the M/DEC1 register.