ADC32RF45EVM: Aligning the data from JESD204b RX IP in FPGA

Roja Veereddy

Intellectual 320 points

Part Number: ADC32RF45EVM
Other Parts Discussed in Thread: ADC32RF45, LMX2582

Hello sir

We are doing ADC32RF45 transmits the data to polarfire FPGA.

Input RF frequency is 150MHZ

Clock to ADC is from LMX2582

Internal clk frequency is 1536MSPS

LMFS value is 8224

As per these settings, we are getting the data from JESD204b RX IP(which is in FPGA) output .

Each of the data is 32 bit

Please can you suggest us to reconstruct original data from these four lanes.

How the sampling data is giving all lanes.

please, help us to reconstruct the data which coming from JESD204b IP(FPGA).

Thanks

Roja Veereddy

over 4 years ago

0 Vijayendra Varma Siddamsetty over 4 years ago

TI__Genius 10805 points

Hi Roja Veereddy,

Frame format for DDC bypass 8224 LMFS mode is shown in Table 5 in datasheet. Here one frame is shown and it is 16-bit wide. As you receive 32 bit wide data from JESD IP, it should contain two frames.

Regards,

Vijay

0 Roja Veereddy over 4 years ago in reply to Vijayendra Varma Siddamsetty

Intellectual 320 points

Hai sir

I have one doubt regarding this.

How can we reconstruct the ADC data from these 4 lanes.

which lane will come first and how many samples it is taking, with the sequence of samples how we can reconstruct the data.

Please, kindly help us to resolve this.

Thank you

Roja Veereddy

0 Vijayendra Varma Siddamsetty over 4 years ago in reply to Roja Veereddy

TI__Genius 10805 points

Hi Roja Veereddy,

In the frame format notation, A₀, A_1,A₂and A₃are in the sample order.

For channel A, sample order is lane 0 (DA0) sample (denoted as A₀) followed by samples (A_1,A₂and A₃) from lanes 1 (DA1), 2 (DA2) and 3 (DA3).

It is the same way for channel B from lanes DB0 to DB3.

Within each frame in one lane, each 14-bit sample is spread across two octets. First octet has 8 MSB bits of sample i.e [13:6]. Second octet has 6 LSB bits i.e [5:0] followed by 2 zeros (00).

Regards,

Vijay

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ADC32RF45EVM: Aligning the data from JESD204b RX IP in FPGA