Other Parts Discussed in Thread: ADC32RF45, LMX2582
We are doing ADC32RF45 transmits the data to polarfire FPGA.
Input RF frequency is 150MHZ
Clock to ADC is from LMX2582
Internal clk frequency is 1536MSPS
LMFS value is 8224
As per these settings, we are getting the data from JESD204b RX IP(which is in FPGA) output .
Each of the data is 32 bit
Please can you suggest us to reconstruct original data from these four lanes.
How the sampling data is giving all lanes.
please, help us to reconstruct the data which coming from JESD204b IP(FPGA).