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ADS4245-EP: LVDS DDR Data Timing

Mustafa Su1
Prodigy 40 points
Part Number: ADS4245-EP

Hi, 

Can you answer following:

1) In the datasheet Figure 4 and Figure 5 has difference:

    Figure 4: Odd bits are shown at rising edge of CLKOUTP.

    Figure 5:  Even bits are shown at rising edge of CLKOUTP.

    Which one is true?

2) For data outputs, given th ( hold time) is same for all given frequencies in Table 2, bu setup time gets wider with decreasing frequencies.

    Is Hold time are all same (min: 0.33 , typ=0.6 ns) for all frequencies? 

    We are using the device at 10 MHz. Why doesn't hold time gets wider at lower sampling frequencies?

    If the hold time is always 0.33 ns, isnt it a contradiction with center aligned source synchronous data transfer?

    Do we need to add a phase shift to the clkout signal in FPGA in order to center the data eye?

Mustafa

  • 0
    TI__Mastermind 18095 points

    Mustafa:

    Figure 5 is correct.  Figure 4 has a typo.  The diagram should start with even bits.

    Yes, hold time is specified as constant across all frequencies.  I am not privy to the mechanics of digital circuitry.  Other devices in the ADS4xxx family behave similarly up to 125 MSPS.

    Hold time specifies time data must be valid after output clock transitions.  A small value does not impact center aligned synchronous transfer.  No need to delay FPGA clock.

    --RJH

  • 0 in reply to RJ Hopper
    Prodigy 40 points

    Thank you. We had some problems at high temperature and we got into details. So we are sure that even bits are clocked at rising edge.

    So another question is i think setup time will get increase as frequency get decreases. For 25 MHz , i calculated as setup time should be minimum around 18 ns. 

    by assuming that;

    tco_min = th

    tco_max=t_period/2-tsetup

    for given frequencies tco_max is around 1.7 ns. 

    I think we can assume that tco_max is also constant across all frequencies, right?

    It right, then for 25 MHz, we can see that tsetup can be assumed 18 ns for 25 MHz,right?

    Thanks.

    Mustafa