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AMC1306M25: AMC1306 output duty not changing

Part Number: AMC1306M25
Other Parts Discussed in Thread: TLC04

Good Afternoon

I am using an AMC1306M25 isolated amplifier, interfacing to a 4th order butterworth filter to generate an analogue output voltage. I am measuring a changing voltage between AINP and AINN in the 10's of mV region, however I do not see this on the DOUT pin.

I am clocking at 5MHz, and on the DOUT pin I do not see a stable duty cycle. I see pulse widths of 200ns and approx 400ns.

My schematic is below

What am I missing?

  • Hi Matthew,

    One thing missing is your schematic - it did not make it through the posting process.  Could you please re-send?  The AMC13306M25 is a modulator, so you won't actually see a PWM type response, it's going to be a higher or lower one's density based on your input voltage.  At 5MHz, a high width of 200ns is a singe 'one' while a high width of 400ns is two 'one's' in succession.

  • Tom,

    Thanks for the reply, I am replied with my schematic. So I am seeing effectively a single '1' followed by a single '0' then 2 '1's in succession. I should be able to get a scope trace tomorrow. Unless my schematic yields any answers!


  • Hi Matt,

    Thanks for re-sharing your schematic.  To be honest, I don't think this is going to work the way you expect it to.  I've never used the TLC04 myself but going over the datasheet, I don't see how it's going to be able to keep up with the bitstream from the AMC1306M25.  Not sure how familiar you are with delta-sigma ADC's, but the AMC1306 is essentially the front end of a typical delta-sigma converter.  The output bit stream in a typical DS ADC is digitally filtered inside the chip and then gives you a digital output word that represents the average weight of the bit stream that comes from the front-end modulator.

    Since the AMC1306 is just the modulator, the output bit stream is generally processed by an FPGA or DSP with the modulator filtering functionality built in (like the F23879D DSP you spoke to Manoj about a few months back).  They take that 5MHz stream of one's and zero's and accumulate/decimate the data down to some slower data-rate with a time averaged representation of the analog input signal.

  • Tom,

    Thank you for your reply. Doing some more work into delta-sigma modulators I realised that what I was seeing could be correct (I thought originally it would be a 50% duty at the clock frequency). I found that the TLC04 gave me a very oscillatory response, so replacing this with a simple RC filter reconstructed the signal that I was expecting, and to my calculations. 

    The long term plan is to use the F2879D DSP as discussed with Manoj which will give a more accurate reconstruction. 

    Thanks again for your help