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ADS7052: Calibratied result of ADS7052

Part Number: ADS7052
Other Parts Discussed in Thread: REF1933

Hello TI member :

  I am trying to build a 14 bit environment by using ADS7052, could you help me to confirm whether my calibration flow was wrong or correct ?

  My test flow are showed below, thank you for reading it patiently!

  Test condition:

  AVDD = REF1933 = 3.3V

  DVDD = REF1933 = 3.3V

  SCLK ~ 333.3 kHz 

Purpose of this testing :

  Check whether my calibrate function work correctly


  Figure.1 is my "power up calibration" result, SDO from ADS7052 return code '0' while host provide 24 clock ( SCLK ~ 5.6 kHz )


Figure.1: Power up calibration

  For more check on my calibration flow, figure.2 is my "offset calibration during normal operation" result.

  Since my capture result was operated with VINP tie to AVSS , so SDO from ADS7052 return code '0' at first frame ( 18 clock ) seems correct.


  Figure.2 : offset calibration during normal operation

  After these two flow done, I tie ADS7052's VINP to REF1933's BIAS pin that provide AVDD / 2 and start to enter in CONV state to fetch transfer results with SCLK ~ 333.3 kHz.

  Figure.3 is my calibrated results but it's seems didn't return  '8192' as main code but '8176' ...... 



  Figure.3 : Calibrated result with AVDD = REF1933 = 3.3V, DVDD = REF1933 = 3.3V, SCLK = 333.3 kHz , sample rate < 100 Ksps

  My question :

  1. Is the calibration flow have wrong ? ( such as power up calibration may not work correctly after REF1933 is being enable due to It's not the power up state ? ) 

  2. From ADS7052's datasheet, figure.21 shows code '8125' as main code. Is the figure.21 as un-calibrated result ?

  Thank you for your help.



  • Hello Chen

    Your SPI looks correct to complete the offset calibration. I will point out that you do not need to change the AINP input. The device internally disconnects the input signal, thus there is no need to make any changes in the hardware for offset calibration. 

    The reference would need to be settled and stable for the offset calibration to result correctly. Also, note that the reference voltage level directly impacts the offset calibration result. Meaning if the AVDD is at 3.4 instead of 3.3V, this will be reflected in the result. 

    I will look into the data sheet question, this is a valid point. 



  • Hello,

    After looking into this, the input signal for the histogram is not a precision signal nor ratiometric to the input. this is why the value is not at the mid code. The goal with the histogram was more focused on demonstrating the spread and not the code value.

  • Hello Cynthia:

      Thank you for sharing me that the meaning of figure.21.

      I'd like to check the meaning about demonstrating the spread of code.

      Is that means if I want to achieve DNL about +/- 0.3 LSB , the spread of code will like  figure.21 shows or the mid code is more centralized  ?

      If the mid code will be more centralized, is there something I need to check such as the frequency of SCLK or .... ??

      Thank you !