DAC3161: About DAC3161 CLK signal question

Jimmy WANG

Expert 2895 points

Part Number: DAC3161

Hi Team,

Can I use one CLK signal provide to 1:2 Buffer and in to DACCLKP/N & DATACLKP/N?

DACCLKP/N & DATACLKP/N

over 3 years ago

0 Neeraj Gill over 3 years ago

TI__Mastermind 20541 points

Hi Jimmy,

Generally DATACLK is generated in the FPGA and sent to the DAC along with the DATA. The DATA and DATACLK will need meet setup and hold time to properly latch data in the DAC. Generally DACCLK and REF clock for the FPGA( used to drive DATACLK) are from same source. The EVM schematic for further info.

Regards,

Neeraj

0 Jimmy WANG over 3 years ago in reply to Neeraj Gill

Expert 2895 points

Hi team,

thanks for your reply.

but I want to know. Could I use same clock signal through 1:2 buffet provide to DACCLKP/N & DATACLKP/N?

thanks!

0 Neeraj Gill over 3 years ago in reply to Jimmy WANG

TI__Mastermind 20541 points

Hi Jimmy,

Yes you can use it. You will have to make sure you also send another copy of the data clock to the FPGA to generate the data. So that you can meet the setup and hold time easily.

Regards,

Neeraj

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DAC3161: About DAC3161 CLK signal question