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ADS7057: Setting sampling rate of the ADC through the SPI interface.

Daniel Arapalo
Prodigy 40 points
Part Number: ADS7057

I have an application requirement to design a data acquisition recorder with a 500KHz sampling rate using the ADS7057 connected to a STM32 Chip. My input signal is a single ended bipolar signal and I'm trying to use the application note reference here . 

  • From the datasheet, typical conversion time is given as 18 x tclk where tclk is 16.66ns (which I guess is a 60MHz SPI line), minimum acqusition time is 95ns. if sampling frequency is conversion + acqusition time, This gives typical conversion time to be 95ns + (18 * 16.66 ns) which is the maximum sampling frequency of 2.5MHz. If I want to set it to 500 KHz,  Do I just increase the conversion time by reducing the speed of the SPI line or just a set an interrupt on the controller for the given sample rate?

  • In page 3 of component selection for the reference, Rfilt and Cfilt were chosen for a specific input signal and sample rate. (250KHz and 2.5Msps) using the analog engineer's calculator. Would these values still be applicable for say, a 190Khz signal with as sample rate of 500KHz?

  • 0
    TI__Mastermind 24940 points

    Hello, 

    There are to ways to decrease the sampling rate for this device 1. Extending the Acquisition time 2. Decreasing the Clock rate

    The sample rate is defined as the time between two falling CS edges, this is the cycle time. To extend the acquisition time, you keep that clock rate the same and keep CS high for longer time. The other option, is decreasing the clock rate. To do this, it based on the desired sample rate of 500KSPS = 2us, then calculate SCLK = (2us - 95ns) /18 = ~105ns, this would be your clock period, or in hertz it would be ~9.5MHz

    The Analog Eng. Calculator is a free tool available online . you can download and check the Rfilt and Cfilt values based on any sampling rate.