ADS52J90: PRBS on JESD lanes

Michael,

i attached our FPGA code in another post. while our FPGA 3rd party is not supporting the code. so the code is provided as is. 

i would say that PRBS may introduce complexity in this debug.  RAMP pattern may be the easiest , after you give a TX_TRIG to align all digtial circutis. 

i attached the PRBS description if you plan to go that route. 

Thanks!PRBS in the ADS52J9x AFE581x 2x family.pdf

Hello Xiaochen (Sean)Xu,

The problem is that the toolkit for the transceiver does not recognize a ramp pattern. It needs a PRBS to verify if the data is correct.

Can you please answer my questions regarding the prbs in my previous post.

Best regards,

Michel Wouters

Michel, 

we will check on our side on the JESD PRBS pattern and come back next week. we usually just use the RAMP pattern and JESD204B IP can recongize it . 

I also suggest you talking to FPGA vender. Our EVM configuraiton file may be the best for the setting the ADS chip. 

Thanks!

Xiaochen (Sean)Xu,

Any update yet?

Best regards,

Michel Wouters

Michael, we checked some

The current PRBS modes specified in the datasheet are inserted in the transport layer of JESD where the pattern passes through 8b/10b encoding. The receiver must have 8b/10b decoder in-order recognize the PRBS pattern.

you may be asking for PRBS pattern inserted at PHY layer where it doesn’t go through 8b/10b encoding. 

you can see if this sovles your mismatch? 

 Thanks!

Xiaochen (Sean)Xu,

The PRBS checker in our transciever block is placed before the 8b/10b decoder. Is it possible to set the adc in a mode that it does not use the 8b/10b encoding for the prbs? I can't find anything in the ADS52J90 datasheet on this.

Best regards,

Michel Wouters