Hello,
I'm driving the ADC using a system that can only change the output pin states synchronously to the falling edge of the SCLK clock. The SCLK is not stopped with the #CS going high, because other devices need to be scanned with same clock in parallel.
Now, the datasheet states:
"When CS is brought high, SCLK is internally gated off. If SCLK is stopped in the low state while CS is high, the
subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track
mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC
enters the track mode on the first falling edge of SCLK after the falling edge of CS."
What would be the behavior if both #CS and SCLK are changing at the same time? Would it be unpredictable, or is the previous value of SCLK (high) still in effect when #CS going high is recognized?
Any hints are highly appreciated.
Ralf