**Part Number:**ADC3660

We are using the ADC3660 in one of our new designs, and are having difficulty trying to calculate/specify the latency and propagation delays through the device.

We are driving DCLKIN and CLKP with synchronized, 40.96MHz clock signals. We are configuring the device for 16-bit data output, complex x16 decimation, and SDR output clocking. If I understand the datasheet correctly, the ADC3660 should sample the input signal on 16 consecutive clock edges for decimation into a single output value; with SDR output clocking, a single 16-bit output value will require 16 DCLK cycles (aligned with FCLK). Therefore, since DCLKIN and CLKP are synchronous and running at the same 40.96MHz frequency, we should be sampling and decimating 2.56 Msamples/second, and outputting complete 16-bit data values at the same rate. Oscilloscope measurements seem to confirm this throughput.

Unfortunately, we are unable to accurately determine the delay between the time when the input signal is sampled and the time when the corresponding decimated output value is clocked out of the ADC. If Samples N through Samples N+15 are being captured and decimated into the output value DA[15:0], how do we determine the consistent delay between the CLKP edge that captures Sample N and the DCLK edge that propagates DA[15]?