ADC12D1600: Test pattern output error

David Jones4

Part Number: ADC12D1600

I'm probing the output terminations (100ohm res) of the data channel LVDS pairs, when the ADC is configured in test pattern mode.

It doesn't seem to match what i'd expect from the datasheet, for instance, the Output of DQd(11-9) is cycling [011,100, 011, 100] when i would expect it to be [111,00,111,000].

I've double checked the routing for polarity errors. All I can think of is maybe the ADC is for some reason in 2-s complement mode, and this affects the test pattern output (i don't think its supposed to according to datasheet).

Any ideas?

Thanks, David

over 3 years ago

0 David Jones4 over 3 years ago

Prodigy 110 points

Note, ECE is high so I would expect it to be in binary offset, not 2-s complement mode.

David

0 David Jones4 over 3 years ago in reply to David Jones4

Prodigy 110 points

Probing at the fan-out from the ADC shows the same, so its not a mis-matched routing-length issue.

0 Rob Reeder over 3 years ago in reply to David Jones4

TI__Mastermind 24350 points

Hi Dave,

Thanks for the follow on reply's.

Unless the pin mapping is off, I cannot think of a reason that the bits would be off, different from expected.

Can you please double check that and let us know?

Have you tried another board to make sure the same is happen for consistency from board to board?

Also, if ECEb pin is logic high then the part is in pin control mode. In that mode, it is impossible for the part to be in 2’s complement output.

Regards,

Rob

Data converters

Data converters forum

ADC12D1600: Test pattern output error