Hi Team,
My customer has a question on the ADC34J45. They are trying to characterize the JESD link between FPGA and the ADC, and would like to know if they can bypass 8b/10b encoding when they chose PRBS15 test pattern in the transport layer. The FPGA has PRBS pattern detectors *before* 8b/10b encoding. We understand this could be a problem for DC balancing of the datastream, but it allows for some level of testing the link.
Thanks,
Mitchell
