Hello team,
Could you please help us to address the DPOT setting issue?
The output doesn't look linearly changes.
In my use case, SCLK = 5MHz and DPOT value is sequentially updated in 200kHz frequency.
In the wrong setting, the LSB is not correct. When incrementing DPOT value, the output sometimes goes up and down.
When this issue is happening, SPI timing looks a little behave a little suspicious.
In the D/S Figure 16, t_CS1 is shown. t_CS1 gets negative when the issue happens (meaning CS rising edge asserts when SCLK=H).
Note that TCSH has 1 clk duration.
#1. In the D/S, t_CS1 requirement is not specified. Does t_CS1 or other timing have any limitation? What do I need to take care?
#2. When T_CS1 gets negative, it looks like the SPI disable is failed because after this event was happened, the output reflects the SDI input under CS=H.
I assumes DPOT is enabled when correct T_CSS is confirmed.
On the other hand, could you please let me know when the timing requirement to disable the DPOT?
#3. Could you please let me know the consideration to update the DPOT with 200kHz frequency?
What debugging action do you recommend?
Regards,
Itoh