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TPL0501-100: SPI communication failed?

Part Number: TPL0501-100

Hello team,

Could you please help us to address the DPOT setting issue?

The output doesn't look linearly changes.

In my use case, SCLK = 5MHz and DPOT value is sequentially updated in 200kHz frequency.

In the wrong setting, the LSB is not correct. When incrementing DPOT value, the output sometimes goes up and down.

When this issue is happening, SPI timing looks a little behave a little suspicious.

In the D/S Figure 16, t_CS1 is shown. t_CS1 gets negative when the issue happens (meaning CS rising edge asserts when SCLK=H).

Note that TCSH has 1 clk duration.

#1. In the D/S, t_CS1 requirement is not specified. Does t_CS1 or other timing have any limitation? What do I need to take care?

#2. When T_CS1 gets negative, it looks like the SPI disable is failed because after this event was happened, the output reflects the SDI input under CS=H.

I assumes DPOT is enabled when correct T_CSS is confirmed.

On the other hand, could you please let me know when the timing requirement to disable the DPOT? 

#3. Could you please let me know the consideration to update the DPOT with 200kHz frequency?

What debugging action do you recommend?

Regards,

Itoh

 

 

 

  • Hi,

    Can you please post your SPI transactions with /CS, /DIN, /SCLK?

    You can keep t_CS1 as 15ns( min)

    DPOT will be disabled for any write operation, the moment you take CS signal high. Previous write will be updated immediately if the frame was valid.

    you can have SCLK idle state as high always.

    after the eighth SCLK you can keep SCLK high after CS goes high, this way we can be sure that SPI frame is valid.

    DPOT will be enabled for transaction after t_CSS is confirmed.

    Regards,

    AK

  • Hello AK-san,

    Thank you so much for prompt response!

    Please find the SPI transaction waveform from the internal link here.

    What can happen when the timing violates the 15ns minimum t_CS1?

    Could you please let me know the specific condition and timing requirement when the frame gets valid?

    About the eighth SCLK you mentioned, do you mean rising or falling edge?

    Regards,

    Itoh

  • Hi,

    Please find the timing diagram below.

    Please note that data is latched on the rising edge of SCLK as per the datasheet.

    CS going high to SCLK going high min is 15nS. you can keep the SCLK low after 8 clock pulses, no problems. Its the minimum spec. 

    if you violate this spec, second frame will be invalid. First frame will be still valid.

    I hope this will be clear.

  • Hello AK-san,

    OK, I understand the t_CS1 of the attached transaction violates the minimum requirement. Will check it with my customer.

    Last time, you mentioned I can keep SCLK low after eighth SCLK pulse in the previous reply. But in the time before last one, you mentioned I can keep SCLK high.

    You mean I can keep SCLK low after the eight SCLK, and then I can assert SCLK high and keep it after /CS goes high, correct?

    Also, will the SPI frame be valid right after the eighth SCLK RE?

    Most importantly, do you think the output linearity result of the sequential increment test (200kHz) can be non-linear when the transaction violates the t_CS1 requirement?

    Regards,

    Itoh 

  • Hi,

    Either way is fine.

    You can keep SCLK idle state high or low, doesn't matter.

    Idea is keep CS low for 8 SCLKS.

    Coming back to your last question, if the frame is valid and code vs DPOT resistance should be linear.

    Regards,

    AK

  • Hello AK-san,

    We found that the linearity issue is not related to the t_CS1.

    In the error operation, the output is updated after the first pulse and /CS is low.

    Please find the waveforms and legends from the internal link here.

    Could you please help us to address this issue?

    What do you think the cause of the update after the first clock?

    Regards,

    Itoh

  • Hi,

    This looks very interesting, Is this repeatable? Can you probe the device supply also ( in ac couple mode) when this issue happening?

    I just want to check for any glitch in the device power supply.

    Regards,

    AK