My design requirement is to generate Fout = 37 MHz. from the DDS . DAC 3283 is interfaced to xilinx FPGA. The interface is 8 bit LVDS.
DDS sampling clock is 96MHz.
DAC clock is 192 MHz.
Data clock is 192MHz..
Can i run DDS sampling clock at 192MHz to get the Fout as 37MHz?
Thanks in advance