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ADS5463: Can we skip to checking DRY pin?

Furkan Fehmi Sefiloglu
Expert 3118 points
Part Number: ADS5463

Hi Team, 

This is customer request, can you please advise:

"

1-) We are getting ADS5463EVM from Texas. This 500 MSPS contains an adc. But we will work with 100 MHz. So adc will work faster than us. But in the adc's datasheet, the clock input sample rate is specified as 20 MSPS to 500 MSPS. In this case, can we adjust the speed of this adc with the CLK that we will apply to ADC according to our 100 MHZ processing speed so that we do not miss data. Otherwise, if ADC works with 500 MSP continuously, we will be able to get 1 data in 5 data of adc, right?


2-) ADC has DRY (data ready) pin and signal. We need to check this pin to get the data. But there is an expression such as "It is recommended to use the DRY signal to capture the output data of the ADS5463" in the datasheet, so if we do not check the DRY signal, can we get the data properly by applying the CLK signal?

"

Thanks in advance

Best Regards

Furkan Sefiloglu

  • 0
    TI__Guru* 91947 points

    Furkan,

    For #1, you are correct.

    For #2, you do not need to use DRY to capture data. Whatever clock source you do use, you must meet the setup and hold time requirements of the device used to capture the data with respect to this clock source. This will be hard to do with the ADC running at 500MHz, but since you mentioned you will be sampling at 100MHz, this will provide more margin to work with. You may have to adjust the delay of either the data or the clock used to capture the data to meet these requirements. It is recommended to use DRY if possible.

    Regards,

    Jim  

  • 0 in reply to jim s
    TI__Expert 3118 points

    Hi Jim, 

    This is customers feedback, can you please check and advise:

    "

    Jim said you are correct to the 1st question, but there we asked him a question "can we adjust the speed of this adc with the CLK that we will apply to ADC according to our 100 MHZ processing speed so that we do not miss data" did not answer. Or should we understand that if he answered, we can adjust the ADC speed between 20 MSPS and 500 MSPS ???? I could not understand that part.


    I read your comment to the second question. He stated that there is no need for the dry signal there. It is already stated as recommended in its document. However, Whatever clock source you do use, you must meet the setup and hold time requirements of the device used to capture the data with respect to this clock source. This will be hard to do with the ADC running at 500MHz. Here, we will produce CLK with FPGA-based sbrio9629 card and get the data in parallel with 12 DIO pins of the same card, that is, we will work in synchronization, in this case, we will automatically meet the setup and hold time requests of our NI sb rio9629 card with the software we have made. Still, in the last part of his answer, Jim stated "it is recommended to use dry if possible".


    We have not avoided checking DRY pulses, in fact, our problem is that when I check the DRY signal, the 4th or 5th DRY signal has already produced or will be about to produce ADC with a speed of 500 MSPS during the time that will pass until we receive the data with CLK at 100 MHz speed. In this case, if I try to get the data with CLK during the GENERATION of the 4th or 5th DRY signal from the ADC, will it give me a HALF code that does not correspond to the real voltage? We are trying to understand this issue? If we can adjust the working speed of ADC between 20 MHz and 500 MHz with the clk pulses we will produce, I can generate my clk pulses with 100 MHz and I can get a 12 bit data at 10 ns by checking my DRY signal without loss of code. Because in the datasheet, it is talking about a clk between 20 MSPS and 500 MSPS, so I am on this topic.

    "

    Thanks in advance

    Best Regards

    Furkan Sefiloglu

  • 0 in reply to Furkan Fehmi Sefiloglu
    TI__Guru* 91947 points

    Furkan,

    The customer can use any frequency between 20MHz and 500MHz for the ADC clock. I would not suggest using the clock source from an FPGA as the phase noise of this clock source will probably decrease the performance of the ADC.

    Regards,

    Jim