ADC16V130: RE: ADC ENOB

Hi Naveen P,

When terminating the input, is the common mode voltage (V_RM = 1.15V) still present on both VIN- and VIN+?

Can you please share a schematic of the ADC and ADC analog input driver?

Best Regards,

Dan

Hi dBrock,

Thanks for your response. While terminating input, I measured across the Vin p/n pins I am getting 30mV(measured in diff probe) in all the ADC. We are using 6 ADCs in our design.

While I validate the ENOB for all the ADC's only two ADC have 12 bits ENOB and remaining all the ADC 's are 10 bits

So i need to improve the system all the ADC ENOB to at least 12 bits. Is there any test to be performed to improve the ENOB.

Is there any possible way for terminating terminating the ADC input pins, as i mentioned earlier our input crosses the multiple stages in our board or any possible to calibrate the ADC.

Thanks,

Naveen P

Hi Naveen P,

In order to better assist, it would be helpful to have a diagram/schematic of the analog input.

When you are measuring 30 mV (differentially) across the +/- Vin pins, does that mean that the + pin has 1.15V and the - pin has 1.12V? I am just trying to ensure that the common mode voltage is set appropriately on all of the ADC analog input pins (Vin +/-) when you are calculating the ENOB. As mentioned earlier, is the ADC providing the common mode voltage to the differential amplifier, or is the common mode being generated another way?

Here is a schematic from the ADC16V130 Evaluation Module. Is this a similar implementation to your analog front end (minus the differential amplifier)? Where are you grounding the input in relation to this schematic (see red where you could terminate while maintaining common mode voltage at analog input pins)?

How is the ADC output data being collected and analyzed to ensure that the ENOB is 12 bits? For 10 bit ENOB you are seeing, does this mean the SNR is about 60 dBFS (SNR=Nbits*6.02+1.76)?

Best Regards,

Dan

Dear Dan,

Thanks for your response. Please find the attached ADC and clock section Schematics for your reference.

For ENOB measurement, Our ADC outputs are connected to FPGA, We are measuring the ENOB via the signal tap file from FPGA to ADC outputs.

As per your above suggestion, I have tried to connecting Vin pins through 0.1uf to ground still the bit toggling remains same. 

our aim is to improve the system all the ADC ENOB to at least 12 bits. Please do the needful.

Thanks

Naveen P

ADC1_Schematics flow.pdf

Hi Naveen P,

Thank you for sharing the schematics. In order to further assist, can you please share the layout that would include the inputs/output for the ADCs including to the FPGA?

Here are some questions from schematic review:

The VRN and VRP pins should not be used to sink/source current. The datasheet (page 3) calls out that these pins should be connected together with 0.1uF and 10uF capacitors. They should then be tied to ground with a 0.1uF capacitor. From the schematic, it is not clear if this is being done since the nets go off page. This could be a critical issue, so please verify these pins are not being loaded (other than the capacitors mentioned).

For the ADC LVDS data coming to the FPGA (for all 4 ADCs), is there a 100 ohm parallel resistor for each LVDS pair, or is 100 ohm termination enabled in the FPGA? Are each LVDS pair length matched to the FPGA?

In regard to the ADC clocks, please verify that the clock amplitude (shape) is the same at all 4 ADC clock inputs.

Looking at U76 (THS770012), the output impedance of U76 (set by R716 and R717) is 50 ohms differential, but look like there is 200 ohm differential termination (R610 and R611).

Additional Comments:

When verifying ENOB, are you using a sinewave input? Besides an ENOB difference, what is the shape of the waveform?

With just the common mode voltage applied and the analog input pins (no external input), what is the DC voltage at each analog input pin? What is the code value captured in the FPGA? This value should be similar for all 4 ADCs.

With an input applied (sinewave) to all 4 ADCs, can you capture the ADCs data in the FPGA and see compare against the 12 bit ENOB ADCs and 10 bit ENOB ADCs? I would be looking at the lower 4 bits to ensure they are being capture in the FPGA correctly.

Best Regards,

Dan

Dear Dan,

Thanks for your quick response. Please find the below points wrt your queries,

• For layout files, let me check with my team and let you know. Once they provide approval I will share the file.
• There is no sink source option for the VRP and VRN pins, we have followed as per the datasheet recommendation. In schematics we have used power net for connecting cap and ADC pin.  
• We have used 100E impedance in ADC output to fpga traces and we have used 100E resistor at FPGA terminating end.
• Please find the attached document all the 6 ADC clock input wave form for your reference.
• For differential termination we have updated with 50E resistor in that path, still the bit toggling remains same.
• Attached bit toggling waveform we have captured in signal tap file form FPGA for your reference.With the terminating the all ADC input we are capture the signals across the Vin_p&Vin_n we are gettingADC Input clock_Bittoggling.docx probe noise alone 2to 3mV in all ADC.
• We are feeding -30,-5,-3 dbm sine wave with the 76.5Mhz frequency we are measured the signals of ADC1-3

Please confirm our method of validating the ENOB is correct if not kindly suggest the proper way to test the ENOB for ADC.

Thanks

Naveen P

Hi Naveen,

Thank you for gathering this data.

The schematic for VRP/VRN ADC pins that was shared did not come through. Can you share this one more time please (attach again)?

When the 75.6MHz signal was measured at the 3 ADCs, was this an oscilloscope probe at the ADC analog input pins, or was this extrapolated from the FPGA data?

From the ADC Bit Toggling Verification, is this how the ENOB is being calculated by counting the toggling bits?

Can you please share the signal tap ADC samples from two of the ADCs, and the sampling rate that is being used? The format of the file can be is txt or csv. I can then import this into HSDC Pro to look at the FFT/Timed domain of the ADC sample data, and understand the SNR/ENOB better.

Best Regards,

Dan

Hi Dan,

I am Devanathan, Naveen is part of my team, We are working together in same team. Please find the VRP &VRN decaps section below.

Actually we are measuring the ENOB using number of bit toggling with zero input condition( ie very low power input signal around -60dBm @76,8MHz IF frequency from signal generator or terminating the IF input that goes to ADC through BPF, Diff. Amp & BPF).

The number of bit toggling are captured in FPGA using Signal TAP. The ADC digital output 16 LVDS pairs and clock output are connected to FPGA. In FPGA, we are observing the number of LSB bits variation for zero or very low input power condition(ie noise floor level condition).

Below are some observations on the Vcm input voltage, number bit toggling for different clock input sources( one is from PLL device(LVCMOS output given to ADC clock pins through balun transformer, another method is directly feeding clock from RF signal generator.  Both case the frequency is at 104MHz)

We also observed the clock waveforms at all 6 ADC clock input pins ( clock source from PLL -LVCMOS) and noticed that waveform is like sinewave form. Is sinewave form type of differential clock accepted for ADC. Because the slope rate of sine wave is less , compared to LVDS or LVPECL type clock waveforms. ADC clock section circuit is already available in Naveen shared schematic file. Please check and let us know whether our method of ENOB verification is correct or not.   We will check with our FPGA engineer how to get the signal TAP waveforms files in txt or csv format from tool. Please suggest better method of verifying the ENOB and SNR of ADCs.

Thanks,

Devanathan

Hi Devanathan,

The images that you shared did not post correctly. Can you please try sharing them again using the "Insert File" icon (paper clip)?

The LSB bits toggling

ENOB is calculated using this equation: ENOB = (SINAD - 1.76)/6.02.

For the ADC16V130, we can insert SINAD from the datasheet (lets use 77 dBFS for 70MHz input). ENOB = (77 -1.76)/6.02 = ~12.5 bits.

We can calculate actual SNR/SINAD using the requested ADC codes (from FPGA signal tap) in our software HSDC Pro, so we can see what SNR you are achieving on each ADC. Idle input will be useful for noise floor performance, but we will also need to see the ADC codes with an input signal applied.

Best Regards,

Dan

Dear Dan,

Thanks for your response. Please find the attached Signal tap csv file and schematics pdf file for your reference.

We have measured the ADC inputs across VinP/N pins with oscilloscope probe, attached waveforms for your reference.

Yes, Bit toggling verification we have counting the toggling bit in ADC output . Is there any other method please suggest.

Attached ADC1 and 2 signal tap csv files for your reference. 

Hi Dan,

Thanks for your support and providing the FFT result and FFT computation procedure.

We will check for the remaining ADCs using HSDC Pro SW and will comeback to you, if any further support needed or queries to be clarified.

I need one clarification that at which edge (falling or raise edge) of input ADC CLK, the Analog VIN input is sample and converted to digital.

Similarly at which edge of Output ADC CLK, ADC data outputs are sent. 

Because, we understand that ADC sampling and ADC outputs are sent at Falling edge of clocks( one clock cycle + clock buffer delay is the difference between ADC sampling and ADC outputs).  At FPGA in our design, we are latching ADC Data(LVDS  signals) at Rising edge of ADC clock received at FPGA.

Please confirm us our understanding is correct or not.

We will check the timing parameters Digital Outputs with respect to output Clock.

regards,

Devanathan

Dear Dan,

Any update or info on the Clock edges used for Digital Data output from ADC.

Because in FPGA, we are using IBUF LVDS buffer to convert the Differential signal to Single ended signal and used rising edge of clock to latch the ADC data output.

So need your confirmation on this.

One more info is required that we tested 6 ADCs used in our design using number of bit toggling.(ie ENOB). 

Below is our observation on 6 ADCs in our design using bit toggling.

As per your FFT analysis on ADC1 signal TAP waveforms, ADC1 has good SNR, SFDR, ENOB parameters. The ENOB result is same as our bit toggling verification.

So if my understanding is correct, then what could be issue for more bit toggling in ADC2, ADC4, ADC5 and ADC6. Please give your feedback on this.

regards,

Devanathan

Hi Devanathan,

The analog input signal is sampled on the falling edge of the sample clock (see note 3 on page 9 of the datasheet). The latency of sampled data to being available at the LVDS digital output data is 11 (sample) clock cycles (page 9 of datasheet).

I would still analyze each of the ADCs sample data to ensure the performance since bits toggling is not necessarily a direct correlation of ENOB since ENOB is a function of SNR/SINAD.

As suggested before, pull the csv data for each ADC (16384 samples) as I provided instructions for in the power point. Once you can determine the actual ENOB/SNR for each ADC with no input applied, I would then apply a full scale sinewave signal to each ADC to ensure that the performance is holding.

From a schematic standpoint, I don't see any discrepancies.

Best Regards,

Dan

Hi Dan,

Thanks for your response. I have simulated ADC with three cases, with terminated input and 90% power level and full scale range.

Please find the attached all the ADC's noise floor measurement PPT for your reference.

Kindly review our test results, Please provide your valuable feedback. 

Thanks

Naveen PADC_Noisefloor_measurement.pptx

Hi Dan,

Please find the attached updated PPT with 6 ADC's noise floor measurements. We have getting all the 6 ADC's ENOB is 12.5 but I have one quarry while we are measuring by using bit toggling method we are observed bit deviations in one ADC to other.(ADC1 and 3 are 4 bits remaining ADC's 6 bits)

So please check our attached PPT and also is there any other method to ensure the ADC ENOB or shall we proceed with our testing with the HSDC pro results.

Thanks

Naveen P

5811.ADC_Noisefloor_measurement.pptx