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ADS124S06: Spikes in the read data

Marcin Caval
Prodigy 100 points
Part Number: ADS124S06

Hi,

I have a problem with ADS124S06.

Device is configured as below in sigle shot mode.

static uint8_t m_tx_buf_CONF_1[]    = {0x42, 0x00, 0x01,    0x43, 0x00, 0x0F,     0x44, 0x00, 0x39,      0x45, 0x00, 0x02};
                                                                            // Conf_1: MUXP = AIN0 | MUXN = AIN1 | PGA_EN = 128 |
                                                                            // Global Chop disable |LL Filter | 100SPS |
                                                                            // REFP0,REFN0 | Internal reference on
static uint8_t m_tx_buf_CONF_2[]    = {0x42, 0x00, 0x23,    0x43, 0x00, 0x0F,     0x44, 0x00, 0x39,      0x45, 0x00, 0x06};
                                                                            // Conf_2: MUXP = AIN2 | MUXN = AIN3 | PGA_EN = 128 |
                                                                            // Global Chop disable |LL Filter | 100SPS |
                                                                            // REFP1,REFN1 | Internal reference on

I read alternately both diferential inputs.

Here is my connection shemat:

 

And here is output:

Which could be the cause of such spikes ?

Marcin

  • 0
    Prodigy 100 points

    When I change configuration to:

    static uint8_t m_tx_buf_CONF_1[]    = {0x42, 0x00, 0x01,    0x43, 0x00, 0x0F,     0x44, 0x00, 0x39,      0x45, 0x00, 0x02};
                                                                                // Conf_1: MUXP = AIN0 | MUXN = AIN1 | PGA_EN = 128 |
                                                                                // Global Chop disable |LL Filter | 1000SPS |
                                                                                // REFP0,REFN0 | Internal reference on, but powers down in power-down mode
    static uint8_t m_tx_buf_CONF_2[]    = {0x42, 0x00, 0x23,    0x43, 0x00, 0x0F,     0x44, 0x00, 0x39,      0x45, 0x00, 0x02};
                                                                                // Conf_2: MUXP = AIN2 | MUXN = AIN3 | PGA_EN = 128 |
                                                                                // Global Chop disable |LL Filter | 1000SPS |
                                                                                // REFP0,REFN0 | Internal reference on, but powers down in power-down mode

    and connections:

    the spikes don't occurred:

  • 0 in reply to Marcin Caval
    TI__Guru** 112725 points

    Hi Marcin,

    The two circuits are much different in operation and with respect to analog settling.  Consider that the reference for the series circuit is basically 1/2  of the Vref output for each bridge (assuming that each bridge is the same) as compared to the full reference voltage of the parallel circuit.  This means that the LSB value of each code will be valued differently for each circuit.  So you should expect to see twice the number of codes in noise as compared to the parallel circuit.

    Analog settling must also be considered as you are using single-shot mode at 400sps (not 100 or 1000sps based on the register settings).  Your block diagram does not indicate any filtering or capacitors that may be involved.

    I would suggest running the serial circuit and looking at just a single bridge measurement and see if this has improvement.  You might also consider continuous mode and collecting data for comparison.  If using this mode of operation is acceptable, you can try toggling between the two measurements but also adding additional delay at the start of conversion.  This can be done using settings in the PGA register (0x03) and adjusting bits 7:5 to extend the delay time.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 100 points

    Hi Bob,

    Thank you for fast reponse,

    1. I am fully aware of the disadvantages of using a series connection of bridges, but this is due to economy - the current consumption of the entire set.

    2. Yes, it is my mistake in //comment section. I am waiting for DRDY after every conversion, so delays are not needed

    3. I try to read only one bridge in series connection - the effect was the same. I will try with contionous mode with extend delay time.

    After checking, I will come back here with my results.

    Best regards,

    Marcin

  • 0 in reply to Marcin Caval
    TI__Guru** 112725 points

    Hi Marcin,

    I need to make sure I am clear.  It is not the delay following the previous conversion but instead the delay required once the START command is issued to start the conversion that requires settling.  The reference will start to draw current after the START command is issued and then the additional delay allows the digital filter to be held in a reset state until released following the delay period as given in the programmable delay register setting.  The default setting is 14 tmod periods.

    It would also be helpful to know the actual circuit as opposed to just the block diagram.  So if you have a schematic you can share it would be helpful.  In particular the input to the reference.  There should be at least a 100nF cap across the reference inputs to help with noise and as a charge reservoir for the reference input.

    Best regards,

    Bob B